Introduction toVLSI Programming Lecture 4: Data handshake circuits

1
Introduction toVLSI Programming Lecture 4 Data
handshake circuits

• (course 2IN30)
• Prof. dr. ir.Kees van Berkel
• Dr. Johan Lukkien

2
Time table 2005
3
Lecture 4

• Outline
• Recapitulation Lecture 3
• Data encoding push and pull handshakes
• Tangram assignment command
• Handshake components handshake latch,
  transferrer, multiplexer, adder
• Handshake circuits Tangram programs fifo
  buffers and shift registers

4
Header handshake circuit
L0 L1
5
Sequencer realization

• Sequencer area, delay, energy
• Area 5 gate equivalents
• Delay per cycle 8 gate delays
• Energy per cycle 10 transitions

6
Handshake signaling and data
push channel versus pull channel
request ar
7
Handshake signaling push channel
req ar
ack ak
early ad
broad ad
late ad
8
Data bundling

• In order to maintain event ordering at both sides
  of a channel, the circuit must satisfy data
  bundling constraint
• for push channel delay along request wire must
  exceed delay of data wire
• for pull channel delay along acknowledge wire
  must exceed delay of data wire.

9
Handshake signaling pull channel

• When data wires are invalid multiple and
  incomplete transitions allowed.

req ar
ack ak
early ad
broad ad
late ad
10
Tangram assignment x f(y,z)
Handshake circuit
11
Four-phase data transfer
?r / br
ba / cr
ca / ?a
bd / cd
1 2 3 4 5
12
Handshake latch

• ? w?? w?? rd wd r??
  r??
• 1-bit handshake latch wd ? wr ? rd ?
  ?wd ? wr ? rd ? wk wr rk
  rr

13
N-bit handshake latch

• area, delay, energy
• area 2(N1) gate eqs.
• delay per cycle 4 gate delays
• energy per write cycle 4 0.52N
  transitions, in average

14
Transferrer

• ? a?? (b?? c??) a??
  (b?? cd bd c?? cd ?)

15
Multiplexer

• ? a?? c?? a?? (cd ad c?? cd
  ?) b?? c?? b?? (cd bd c?? cd
  ?)
• Restriction ?ar ? ?br must hold at all times!

16
Multiplexer realization
control circuit
data circuit
17
Logic/arithmetic operator

• ? a?? (b?? c??) a?? ((b??
  c??) ad f(bd , cd ))
• Cheaper realization (delay sensitive)
• ? a?? (b?? c??) a?? ((b??
  c??) ad f(bd , cd )) delay ad
  ?

18
A one-place fifo buffer
byte type 0..255 BUF1 main
proc(a?chan byte b!chan byte).begin x var
byte forever do a?x b!x odend
19
A one-place fifo buffer
byte type 0..255 BUF1 main
proc(a?chan byte b!chan byte).begin x var
byte forever do a?x b!x odend
?
a
x
b
x
20
2-place buffer

• byte type 0..255
• BUF1 proc (a?chan byte b!chan byte).begin
  x var byte forever do a?x b!x od end
• BUF2 main proc (a?chan byte c!chan
  byte).begin b chan byte BUF1(a,b)
  BUF1(b,c) end

21
Two-place ripple buffer
22
Two-place wagging buffer
byte type 0..255 wag2 main
proc(a?chan byte b!chan byte).begin x,y
var byte a?x forever do (a?y
b!x) (a?x b!y) odend
23
Two-place ripple register
begin x0, x1 var byte forever do b!x1
x1x0 a?x0 odend
24
4-place ripple register

• byte type 0..255 rip4 main proc
  (a?chan byte b!chan byte). begin x0,
  x1, x2, x3 var byte forever do b!x3
  x3x2 x2x1 x1x0 a?x0 od end

25
4-place ripple register

• area N (Avar Aseq )
• cycle time Tc (N1) T
• cycle energy Ec N E

26
Introducing vacancies

• begin x0, x1, x2, x3, v var byte
  forever do (b!x3 x3x2 x2v) (vx1
  x1x0 a?x0) odend
• what is wrong?

27
Introducing vacancies

• forever do ((b!x3 x3x2) (vx1
  x1x0 a?x0)) x2v od
• or
• forever do ((b!x3 x3x2) (vx1
  x1x0)) (x2v a?x0)od

28
synchronous 4-p ripple register

• forever do (s0m0 s1m1 s2m2
  b!m3 ) ( a?m0 m1s0 m2s1
  m3s2)od

29
4-place wagging register

• forever do b!x1 x1x0 a?x0 b!y1
  y1y0 a?y0od

30
8-place register

• 4-way wagging
• forever do b!u1 u1u0 a?u0 b!v1
  v1v0 a?v0 b!x1 x1x0 a?x0 b!y1
  y1y0 a?y0od

31
Four 8?8 shift registers compared
32
Next session lecture 5

• Outline
• Tangram overview
• Compilation Tangram ? Handshake Circuits
• Tools
• Demonstration
• Lab work assignment fifos and registers