A Powerful EDA Solution on Windows

1
A Powerful EDA Solution on Windows
MyCAD
2
Table of Contents

• MyCAD Profile Mission
• Electronic Design Automation Flow
• What MyCAD offers!
• A suite of MyCAD tools
• MyAnalog Station, MyChip Station, MyCell
• MyVHDL Station, MyLogic Station, MyProtor
  Series
• Educational Package
• Others (GDSPLOT)
• MyCAD Roadmap
• Why MyCAD?
• MyCAD Customers
• MyCAD Worldwide Distributors

3
MyCAD Profile Mission

• Complementing UNIX EDA
• Founded in 1994, MyCAD, Inc. is a worldwide
  supplier of Electronic Design Automation
  software. It is headquartered in Technology
  Leading Area, Silicon Valley and has a RD center
  in Seoul, Korea. We have committed ourselves to
  providing quality design tools in terms of IC
  Design/Verification and Full Line-up Educational
  Solution on Windows Platforms.
• MyCAD provides complete solutions for IC/System
  Design on Windows Platforms IC
  Layout/Verification, VHDL Simulation, Logic
  Design, FPGA Prototyper.
• Our priority is to help design engineers create
  innovative products through the most
  cost-effective route with MyCAD tools.

4
Electronic Design Automation Flow
System Design
RTL
Logic Design
Gates
Physical Design
GDS-II
Process Technology
5
What MyCAD offers!
6
A suite of MyCAD tools

• MyAnalog Station
• Analog Circuit Editor, SPICE Netlist Extractor
  Simulator
• MyChip Station
• Custom IC Layout Editor, Verification Tools
• MyVHDL Station
• VHDL Compiler Simulator
• MyLogic Station
• Digital Circuit Editor, Logic Simulator
• MyProtor Series
• FPGA Prototyping Training Kit
  Emulator(MP7000)

7
MyCAD IC Design Solution

• MyAnalog Station
• Schematic Capture, SPICE Netlist Analog
  Simulation
• Provides new models from Berkeley BSIM 4, MOS
  level 6, TFT
• Extracts a various kind of SPICE Netlist
  format
• Standard SPICE, HSPICE, PSPICE, CDL
• MyChip Station
• IC Layout Verification-DRC, ERC, SPICE Netlist,
  LVS
• UPI(User Programmable Interface) Visual
  Basic Script
• Supports DXF(by AutoCAD) Format
• DRACULA Rule File Compatibility

8
MyCAD Educational Solution

• MyVHDL Station
• VHDL Modeling, Simulation Debugging
• Supports IEEE 1076-1987 1076-1993 VHDL
  Standard
• Provides VHDL Wizard, Syntax Coloring
• MyLogic Station
• Schematic Capture/Logic Simulator, Schematic
  Generation from EDIF
• Supports a various drawing modes
• Schematic, Symbol, State Table, Truth Table,
  Logic Equation (Boolean Equation), ROM/RAM Table
• Structural VHDL Netlist Generation

9
And More !!!

• MyProtor Series
• FPGA Prototype System
• Implementation of the design done by MyVHDL
  and MyLogic Tech Mapping into Xilinx (Altera)
  FPGA Device
• MP1100 MP3100
  MP7000

10
MyAnalog Station

• Schematic Capture, SPICE Netlist Analog
  Simulation
• Specification
• SchEd_Analog Schematic / Symbol Editor
• Logic2SPICE SPICE Netlist Extractor
• MySPICE Analog Circuit (SPICE) Simulator
• MyPostProcessor Graphical Simulation
  Analyzer
• Main Feature
• Provides new models from Berkeley BSIM 4, MOS
  level 6, TFT
• Extracts various kinds of SPICE Netlist
  Formats
• Standard SPICE, HSPICE, PSPICE, CDL

11
MyAnalog Station Design Flow
Schematic Circuit
SchEd_Analog
SPICE Netlist
Logic2SPICE
SPICE Simulation
MySPICE
12
MyChip Station

• IC Layout Editor IC Verification
• Specification
• LayEd Custom IC Layout Editor
• MyDRC Design Rule Checker
• LayNet SPICE Netlist Extractor
  Electrical Rule Checker
• MyLVS Layout V. Schematic Netlist Comparator
• CIFGDS CIF / GDSII Translator (Database
  Converter)
• Main Features
• UPI(User Programmable Interface) Visual
  Basic Script
• Supports DXF(by AutoCAD) Format
• DRACULA Rule File Compatibility

13
Whats NEW in MyChip V6.1

• Hierarchical Design Manager
• Real Time Design Rule Checking
• Create Bitmap (or Clipboard)
• Orthogonal Objects Stretch
• Flatten Label Path (with variable width)
• Etc

Distinct Features
More ...
14
Hierarchical Design Manager
New Feature LayEd V6.1
List Mode
Hierarchy Mode
15
Real Time DRC
New Feature LayEd V6.1
No Boolean Operation
lt Layout Design Checking on the fly while a
designer edits the layout gt
16
MyChip Station Design Flow
Layout Data (CIF,GDS,DXF)
Design Rule Check
LayEd
MyDRC
Electrical Rule Check SPICE Netlist Extract
LayNet
Layout Versus Schematic
Stream out (CIF,GDS,DXF)
MyLVS
CIFGDS
17
MyChip Station Structure System
GDS Format .gds, .sf
CIF Format .cif
Technology rule .tec
SPICE from Schematic .net, .cir, .spc, .spi
CIFGDS Database converter
Discrepancy Report .dis
SPICE File extract.1
Summary Text File drc.sum
compare
MyDRC Design Rule Checking
LayNet SPICE Netlist Extractor ERC
MyLVS Layout Versus Schematic
MyChip Database Layout.1
Device Net Shape devshape.1 netshape.1
Open/ Save
Matched device and node match.1
Discrepancy File lvs_bin.1
LayEd Layout Editor
Find net device
display
Error File drc_bin.1
Error File erc_bin.1
display
display
18
MyCell

• Cell Library
• Supports MOSIS 0.35um (TSMCs process tech Files)
  Std. Cells
• Design Rule file, LVS Rule file, Std. Cells
  (over 40 subsets)
• Data book
• Schematic Data
• Layout Data
• Supports MOSIS 0.5um (HPs process tech Files)
• Design Rule file, LVS Rule file

DESCRIPTION BLOCK
D
ESCRIPTION LAMBDA 0.5 MODE FLATTEN SUBSTRATE
pbulk technology layers nwell active pplus
nplus poly contact metal1
SPICE Simulation
Tech. File
Layout
19
MyCAD IDS Design Flow
LayEd
CIF, GDS Format
SchEd
MyDRC
Logic2SPICE
LayNet
SPICE File
MySPICE
CIFGDS
MyLVS
MASK, Chip
20
MyVHDL Station

• VHDL Modeling, Simulation Debugging
• Specification
• MyVHDL VHDL Code Editor, Compiler, Simulator
• WaveForm Editor Automatic Test Bench
  Generator
• Main Feature
• Supports IEEE 1076-1987 1076-1993 VHDL
  Standard
• Supports Text I/O Std Library
• File read/write
• Textio.vhd, Std_logic_textio.vhd
• Provides VHDL Wizard, Syntax Coloring
• Provides various kinds of Debugging Information
  for efficiency

21
MyVHDL Station Design Flow
VHDL Code Modeling
Compile (Syntax Error Check)
MyVHDL
MyVHDL
Test-bench Modeling
Simulation Debugging
WaveForm Editor
MyVHDL
22
MyLogic Station

• Schematic Capture/Logic Simulator, Schematic
  Generation from EDIF
• Specification
• SchEd_Logic Schematic Editor
• Schematic, Symbol, State Diagram, Logic Equation
  Editor VHDL Source Generator
• MySim Logic Simulator
• Wave Form Editor, VHDL Test Bench Generator,
  Logic Simulator
• Logic2EDIF EDIF Netlist Generator
• SchGen (EDIF2Logic) Schematic Generator
• Main Feature
• Supports various drawing modes
• Schematic, Symbol, State Table, Truth Table,
  Logic Equation (Boolean Equation), ROM/RAM table
• Structural VHDL Netlist Generation

23
MyLogic Station Design Flow
Schematic Design
SchEd_Logic
Electric Rule Checker
Logic Simulation
MySIM
EDIF Netlist Generation
Logic2EDIF
24
MyProtor Series(1)

• FPGA Prototype System(MP1000X, MP1100X, MP3100X,
  MP7000)
• MP1000X The Simple FPGA Prototyper
• Target FPGA Xilinx Spartan - XCS10PC843C
•        SPROM Xilinx XC17S20PC - Option
• I/O Interface 7Segment 7, Dip Switch 4,
  Parallel Port,
• 8pin Port(X-Checker
  Cable)
• Oscillator 1Mhz
• Power DC 5V 10V
• Size 10cm X 10cm
• MP1100X More complicate FPGA
  Prototyper
•     Target FPGA Xilinx Spartan II - XC2S30TQ144
•    EEPROM Atmel AT17C010(ROM Writer) Option
•     I/O Interface LCD Display (16x2), 2-digit
  7-Seg3, LED6
• 10-BAR LED, Buzzer,
  VGA / Parallel(DB-25 male) Port
•     Oscillator 25Mhz
•     Power DC 5V, 3.3V, 2.5V

25
MyProtor Series(2)

• MP3100X More complicate FPGA Prototyper
• Target FPGA Xilinx Spartan II -
  XC2S100TQ208
• 
  32KB SRAM2, Serial PROM(Xilinx
  XC18V01/ROM Writer) - Option
• I/O Interface LCD Display(16x2),
  7-Seg.2, 4-digit 7-Seg.2, LED32, Buzzer,
• 
  PS2 / VGA /
  Parallel(DB-25 male) Port
• Oscillator 25MHz
• Power DC 5/3.3/2.5V
• Size 26cm X 18cm
• MP7000 Series The basic HW/SW
  Co-design System
• Target FPGA Xilinx - Spartan,
  Virtex/E(10,0001,000,000gate)
• Altera - Flex Series(10,000100,000g
  ate)
• Atmel AT89C51 MCU (Intel I8051 compatible)
•           128KB SRAM(4x32KB)
• 22.1184MHz system clock, User clock slot
• Function HW/SW system-level co-debugging
  capability

26
MyCAD SDS Design Flow
Schematic Design
VHDL Modeling
VHDL
MyLogic SchEd
MyVHDL
MyLogic SchGen
MyLogic Logic2EDIF
The 3rd Party Synthesis Tool
EDIF Netlist
MyLogic MySim
MyProtor
27
Educational Package

• MyChip ( MyAnalog) Educational Package
• IC Layout, DRC, ERC, Circuit Extraction, LVS
• Circuit Design, Circuit Extraction for Analog
  Design
• Application for Circuit Design, IC Design and
  Verification
• MyVHDL Educational Package
• VHDL Modeling, Simulation VHDL Synthesis
• Application for VHDL Modeling, Simulation, and
  Logic Debugging
• MyLogic Educational Package
• Schematic Capture Logic Simulation, and
  Schematic Generation
• Application for Logic Design, Simulation, and
  Debugging with Prototyper

28
MyChip Educational Package
LVS (MyChip)
Circuit Design (MyAnalog)
Netlist Extraction
Netlist Extraction
By aid of MyCELL /Manually Design
IC Design, DRC ERC (MyChip)
29
SDS Educational Package
FPGA Prototyping (MyProtor)
VHDL Design (MyVHDL)
FPGA Prototyping / Logic Debugging
VHDL Extraction
FPGA Prototyping / Logic Debugging
Schematic Generation
Schematic Design (MyLogic)
30
GDSPLOT

• GDSII Plotting Software for Windows
• Main Features
• Plots very large GDSII files to raster color
  plotters.
• Extremely Fast!
• Supports hierarchical data.
• Sets layer colors, fills and outline color,
  weight and type.
• Plots selected structures and layers.
• Supports text and text scaling.
• Easy-to-use plot setup menus.
• Plots to scale or Fit to Page.
• Uses customized fill pattern tables.
• Plotting engine can be called from scripts,
  Tcl/Tkl or Frameworks.

31
MyCAD Roadmap
MyCAD V6.x VHDL simulator New Verilog
simulator IC tools Real Time DRC
Hierarchical Design Manager
Windows XP
Windows 2000
MyCAD V5.x New VHDL simulator IC tools New
DRC New Spice Simulator Std. Cell
Windows NT
MyCAD V4.x VHDL simulator IC tools New
LVS
Windows 98
Windows 95
MyCAD V3.x VHDL simulator VHDL synthesizer IC
tools Improved DRC New LVS
Windows 3.1
MyCAD V2.x VHDL simulator Analog simulator IC
Layout Verification
MyCAD V7.x!!! (2003) Newly Innovative IC Layout
Editor
MS-DOS
MyCAD V1.x Schematic IC Layout
90
93
96
2000
2001
2002
32
Why MyCAD?

• MyCAD is an entire family of EDA solutions
  developed, marketed and supported by MyCAD, Inc.
  to provide all IC designers a powerful and cost
  effective assistant. We strongly encourage
  everyone to download a FREE demo version of our
  software for an evaluation.
• For further information and/or comments, you may
  contact us at sales_at_mycad.com.

33
MyCAD Customers

• Major customer
• TI, 3M, Intel, Philips, Motorola
• Microchip Technology, Linear Technology
• Canon, Matsushita, Seiko / Epson
• Fuji, Asahi Glass, Glory
• Samsung, ETRI, Hynix, KAIST
• etc

34
MyCAD Worldwide Distributors
Netherland Chip Consult B.V. Tel
31-187-689-169 Fax [phone]Email
pseesink_at_chipconsult.com
Korea Seodu Logic, Inc. Tel [phone]
Fax [phone] Email mycad_at_seodu.co.kr
China Zhong-Rui institute of Computer Applied
Technology Tel [phone] Fax
86-10-68932958 Email piaotx_at_263.net
USA MyCAD, Inc. Tel [phone] Fax
1-408-745-6783Email sales_at_mycad.com
England Maine Associates Tel [phone]
Fax [phone] Email michael_watts_at_ntlwo
rld.com
Japan IVIS Co., Ltd. Tel [phone] Fax
81-45-332-5391 Email sales_at_i-vis.co.jp
India ICON Design Automation Pvt. Ltd. Tel
91-80-527-2030 Fax [phone] Email
iconsup_at_vsnl.com
Taiwan TimeWave International Corp. Tel
886-3-4316770 Fax [phone] Email
timewave_at_ms5.hinet.net
China Stella Systems Co., Ltd. Tel
852-27511956 Fax [phone] Email
eddie_at_stella.com.cn
Singapore Advinno Technologies Private
Limited Tel [phone] Fax
65-6741-9051 Email terry_at_advinno.com
35
The End

• MyCAD Div.
• http//www.mycad.com