ActiveVHDL Applications

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Active-VHDL Applications
2
Presentation Outline

• 1. Introduction
• 2. Design Entry Overview
• 3. Design Management Features
• 4. Simulation Input Methodologies
• 5. Using Stimulators
• 6. Waveform Viewer Features
• 7. VHDL Debugging Features
• 8. Vital Glitches and Delta Cycles
• 9. VHDL Test Bench Overview

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Presentation Outline (continued)

• 10. Creating and Executing Macro Commands
• 11. Visual BASIC Scripting Capabilities
• 12. VHDL Libraries Handling
• 13. Creating FPGA Design with Active VHDL
• 14. Using Active-VHDL with Foundation Software
• 15. Using FPGA Express with Active-VHDL
• 16. ACTIVE-VHDL Summary
• 17. Active-VHDL Resources

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1.1 Why VHDL Simulation?

• Why do I need a VHDL simulator if I can already
  simulate my VHDL macro using my current FPGA/CPLD
  vendor supplied netlist simulator?
• Answer
• FPGA/CPLD vendor supplied products only provide
  EDIF netlist based gate level simulation (i.e.
  Post-Synthesis) of your VHDL macro. If there is
  a problem in the functional description of your
  VHDL source, you have no way to trace/locate your
  error. You can only guess, or use a VHDL
  simulator to pinpoint your design problem.

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1.2 Why VHDL Simulation?

• Below please find several reasons why VHDL
  simulation is becoming so important to the
  development and implementation of your FPGA/CPLD
  designs.
• Large FPGA/CPLD devices - when developing large
  FPGA/CPLD devices VHDL provides a much easier and
  quicker way to enter and verify your design.
  Imagine placing 35,000 flip flops on a schematic.
• Debugging - VHDL source code debugging takes you
  directly to the line of VHDL code that presents a
  conflict in the functionality of your design.
  There is no need to synthesize the code to
  perform a functional simulation.
• Portability - using VHDL as a design description
  language allows for the reuse of VHDL code
  between projects independent of FPGA/CPLD vendor.

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1.3 Why VHDL Simulation?

• Flexibility - a project designed in VHDL can be
  easily customized to allow for VHDL based IP
  cores to be plugged in for system on a chip
  verification
• Universal Language - VHDL has been adopted by
  every major FPGA/CPLD vendor as a standard
  language for entering high density designs. HDL
  design methodologies are the current trend in
  engineering technology.
• Timing Simulation - most FPGA/CPLD vendors
  provide Vital support and SDF for back-annotation
  of timing delays from the fitter/place and route
  tool. These are two key elements to enable a
  VHDL simulator to provide timing simulation
  results.
• Standard for the future - all new EDA tools are
  based on VHDL technology. Using VHDL standard is
  the best guarantee that the tools will be
  available 5-10 years from now (most schematics
  are obsolete in 2-3 years).

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1.4 Aldecs Answer to VHDL

• PC based Win95/NT tool
• Complete IEEE 1076-93 VHDL language simulator
• New generation graphical user interface
• Complete interactive source code debugger
• Integrated graphical design entry tools
• Links to ACTIVE-CAD and Xilinx Foundation
  schematics
• Supports VITAL 95 simulation libraries
• Test bench wizards
• Single process
• WAVES based

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1.5 Graphical User Interface
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2. Design Entry Overview

• HDL Editor
• HDL Wizard
• Language Assistant
• Finite State Machine Editor
• Schematic can be imported from Active-CAD and
  Xilinx Foundation
• Block Diagram Editor in Version 3.5
• Flexible User Interface Configuration

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2.1 HDL Editor

• Multi-file HDL editing, bookmarks, search
• Color coding of HDL keywords
• Integrated Syntax Check option
• Controls VHDL debugging and cross-probing

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2.2 Language Assistant

• Language Assistant provides quick reference of
  VHDL structures
• Templates are optimized for synthesis
• Users can add their own templates

12
2.3 State Machine Editor

• Graphical VHDL state diagrams editor
• Supports Mealy and Moore diagrams
• Generates VHDL code
• Graphical simulation and debugging of state
  diagrams

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2.4 State Machine Terms

• States
• Conditions
• Transition
• Transition priority
• Reset transition
• State actions
• Transition actions
• Default state
• Trap State
• State encoding

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2.5 FSM Generated Code
if CLK'event and CLK '1' then if res '1'
then Test lt Add qlt"0000" qltq1 else
case Test is when Add gt qltq1 if
dir'1' then Test lt Sub end
if when Sub gt qltq-1 if dir'0'
then Test lt Add end if when others
gt null end case end if end if
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3. Design Management Features

• New Design Wizard
• Design Explorer
• Design Browser
• Files Manager
• Hierarchy Structure Navigation
• Resource Files
• Design Settings and Options
• Design Archive/Restore

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3.1 Design Wizard

• GeneratesVHDL designskeleton
• Creates symbolfor VHDL entity
• SupportsHDL and state machine generation

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3.2 Design Browser

• Displays entire design hierarchy
• Allows browsing the design structure
• Locates any design objects, files, libraries
• Invokes documents where objects are defined

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4. Simulation Input Methodologies

• Stimulators
• Graphical Waveform Input
• Test Bench Generation Wizard
• User-defined Test Bench
• WAVES simulation comparison
• Simulation commands in files or console

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5. Using Stimulators

• Stimulator types
• Value - 160F
• Formula - 1 0, 0 5 ns, -r 20 ns
• Hotkey - R
• Clock - 10 MHz, 60 d.c.
• Custom - from waveform
• Predefined - std. Clocks
• Forcing types
• Override
• Deposit
• Drive

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6. Waveform Viewer Features

• Adding/removing signals
• Applying stimulators
• Editing Waveforms
• Printing diagrams
• Copy/Paste to other programs
• Searching, bookmarks

• Expanding, defining buses
• Defining Radix
• Comments
• Measurements
• Multiple cursors
• Displaying glitches
• Analog display

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6.1 Waveform Viewer Window

• Dynamic display of simulation results
• User defined VHDL display types
• Custom coloring and time measurements

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7. VHDL Debugging Features

• Integrated Syntax Checking
• Code execution tracing
• Object value monitoring
• Event List Window

• Line Breakpoints
• Signal Breakpoints
• Watch Window
• Process state monitoring
• Variable editing
• FSM graphical debugging

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8. Delta Cycles
signal X std_logic '0' signal Y
std_logic A process begin wait for 100
ns X lt not X end B process (X)
begin Y lt X after 10 ns end
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8.1 Vital Glitches
WARNING VitalGlitch GLITCH Detected on port O
Preempted Future Value 0 _at_ 261.714 ns Newly
Scheduled Value 1 _at_ 261.749 nsTime 259049
ps, Iteration 2, Instance \UUT\Q_2_INT_FGBLOCK_L
UTRAM_GLUT_OR2.
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9. Why use VHDL Test Benches?

• plays the role of a complete simulation
  environment for the analyzed system (unit under
  test)
• contains both the UUT as well as stimulus
  generator for the simulation
• response checker compares the actual UUT outputs
  with the expected values (e.g. WAVES based test
  bench)
• very large and complex designs can only be fully
  tested using test benches scripts and others
  methods are too cumbersome

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9.1 VHDL Test Bench Overview

• UUT - Unit Under Test
• Stimulus Generator
• transactions, min/max delays, fault conditions
• Verifier
• checking
• reporting
• comparison

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9.2 Single Process Test bench
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9.3 WAVES-Based Test Bench
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9.4 Automatic Test Bench Generation

• Test bench generation for selected architecture
• IEEE WAVES standard support

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9.5 Test Bench Wizard

• Single process
• converts waveforms to Test Bench
• IEEE WAVES
• golden vectors stored in .VEC
• compares functional and timingresults
• user-defined comparison window
• Standard IEEE 1029 library

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10. Design Automation

• Macro command execution
• Implementation (synthesis, place route tools)
• VBA BASIC scripts execution

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10.1 Creating and Executing Macro Commands

• Automate simulation process
• Batch mode verification
• On-Line syntax reference
• Compatible w/ ModelSimTM

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11. Visual BASIC Scripting Capabilities

• Visual BASIC engine and editor included
• Create custom commands
• Access to all tools functionality
• Script debuggerincluded

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12. VHDL Libraries Handling

• Design Libraries
• User-defined libraries
• Standard libraries (IEEE)
• FPGA vendor libraries
• Source code included for some libraries
• Library debugging available
• Graphical Library Manager

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12.1 Library Manager

• Manage library files
• List library contents

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13. Creating FPGA Design with Active-VHDL

• Multiple simulation configurations
• Post Synthesis simulation (EDIF/VHDL)
• Timing verification with SDF files
• Synthesis scripts support
• Implementation scripts
• FPGA/CPLD libraries provided
• Sample designs and interface guides for each
  vendor included

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13.1 Active-VHDL Design Flow
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14. Using Active-VHDL with Foundation Software

• Active-VHDL Link provided in F1.4 software
• Any mixed VHDL/schematic design can be simulated
• Schematics are automatically converted to VHDL
• VHDL files can be modified within Active-VHDL
• Routed VHDL netlist and SDF can be simulated
• Built-in SIMPRIMS and UNISIM libraries
• Support for LogiBLOX and LogiCORE models

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14.1 Active-VHDL works with Active-CAD
Synthesis
NET2VHDL
FITTER
VITAL, SDF
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15. Using FPGA Express with Active-VHDL
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16. ACTIVE-VHDL Summary

• New generation VHDL design tools
• All tools integrated in one environment
• High performance simulation
• Extensive VHDL debugging capabilities
• For beginners and experts
• Competitive prices

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17. Active-VHDL Resources

• Http//www.aldec.com/activevhdl
• 30-days Evaluation
• On-Line Documentation
• EvitaTM Interactive Tutorial
• Active-VHDL Series Books (1..4)
• 1-800-487-8743 Hotline

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Active-VHDL

• Lab 1
• Training Guide

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Lab 1 Outline

• 1. Creating a Behavioral Design
• 2. Creating CNT_BCD module
• 3. Simulating with the waveforms
• 4. Simple Debugging Features
• 5. Using Test Bench Wizard
• 6. Creating and debugging FSM
• 7. Creating top level in Active-CAD

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1.1 Creating a behavioral design

• The training is based on a simple frequency meter
  design with BCD counter and 7-segment LED
  display.
• The method of measurement is to compare input
  signal frequency with a reference clock signal
  that is slower then measured signal.
• To measure the input frequency you need to set
  START signal to 1 logical value and hold it,
  setting START back to 0 logical value finishes
  the measurement and resets the meter for the next
  measurement cycle.
• The design contains 3 blocks described in
  behavioral VHDL code.
• The design is then synthesized and implemented in
  XILINX FPGA.

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1.2 Creating a behavioral design

• The entire design is described by the following
  diagram

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1.3 Creating a behavioral design

• The following blocks are used in the design
• HEX2LED - 7 segment display converter
• CNT_BCD - 4 decades BCD counter
• CONTROL - frequency meter control state machine

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1.4 Creating a behavioral design

• This section will show the following operations
• How to use New Design Wizard to create new design
• How to use New Source File Wizard to create
  source files
• How to create your own VHDL code
• Basic operations in Design Browser
• Basic operations with Language Assistant

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1.5 Creating a behavioral design

• On the File menu click New Design to invoke the
  New Design Wizard window
• In the Type the design name field, enter
  FREQ_METER
• Click on the Next button to advance to the next
  page

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1.6 Creating a behavioral design

• Select Create an empty design option
• Click on the Next button to advance to the next
  page

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1.7 Creating a behavioral design

• To create new folders use the New Folder option
  from the shortcut menu (click the right mouse
  button in the Design Browser)
• To group files from different stages of the
  design process create the following folders
• FUNCTIONAL
• SYNTHESIS
• PLACE_ROUTE
• TIMING

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1.8 Creating a behavioral design

• On the File menu click New / VHDL Source to
  invoke the New Source File Wizard window
• The Add the generated file to the design box is
  checked, click on the Next button
• In the Type the name of the source file to create
  field, enter HEX2LED

• Click on the Next button
• The HEX2LED component converts 4-bit hexadecimal
  values to 7-bit values that drive 7-segment LED
  display with the common anode. The segment lights
  when the signal value is low.

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1.9 Creating a behavioral design

• Click on the New button, enter the HEX name in
  the Name field and set the range 30 in the Array
  Indexes field by clicking on the arrow button.
  The port direction set as in
• In the similar way add the LED60 port. The
  port direction set as out

• Click on the Finish buttonThe new VHDL document
  with the port list and an empty architecture will
  be created and added to the project.

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1.10 Creating a behavioral design

• To complete the HEX2LED architecture use the
  Language Assistants template
• Invoke the Language Assistant window (the Tools /
  Language Assistant option)

• Select the Synthesis templates / HEX2LED
  Converter item and drag drop it into the VHDL
  editor. You can also use the Use option from the
  shortcut menu.

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1.11 Creating a behavioral design

• In the Language Assistant select the
  SYNOPSYSstd_logic_arith item. You can find it
  in the Language Templates / library, packages
  section
• Add SYNOPSYS library declaration to existing
  HEX2LED code before the entity declaration. The
  METAMOR synthesis tool uses this library.

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1.12 Creating a behavioral design

• Close the Language Assistant window
• Save the HEX2LED.VHD file (press CtrlS keys)
• Close the VHDL editor (File / Close option)
• Use dragdrop feature to move the file into
  FUNCTIONAL subfolder in the Design Browser
• Open the file again by double clicking on the
  HEX2LED.VHD item in the FUNCTIONAL folder and
  compile the file (press the F11 key)
• If there are any errors in the code the erroneous
  line(s) will be underlined by the wavy red line
• The icon color in the Design Browser shows the
  status of the file
• yellow - there are compilation errors
• green - the file was succesfully compiled
• blue - the file was modified and it was not
  compiled after modifications

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2.1 CNT_BCD module description

• CNT_BCD is a synchronous-asynchronous BCD
  counter. It is not recommended to use
  asynchronous modules in the FPGA designs.It is
  used in the training because such a description
  is simpler to create and understand.
• It has the following input ports
• CLK - system clock
• ENABLE - count enable
• RESET - asynchronous RESET
• and output ports
• BCD_A, BCD_B, BCD_C, BCD_D - 4 output tetrads
• FULL - count overflow (9999 is reached) indicator

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2.2 Creating CNT_BCD module

• BCD_CNT has 4 tetrads (CNT10 decade counter). The
  counting range is between 0 and 9999. The device
  starts counting when ENABLE signal is set to
  HIGH. The FULL is active (high state) when 9999
  is reached. When RESET1 the counter is
  reset.

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2.3 CNT10 module description

• The CNT10 decade counter has the following ports
• input ports (std_logic)
• CLK (clock)
• RESET (asynchronous reset)
• ENABLE (count enable)
• output ports
• COUT (std_logic COUT1 when COUNT9 and COUT0
  when COUNTothers)
• COUNT (std_logic_vector (3 downto 0) the counter
  output)

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2.4 Creating the CNT10 module

• Use the New Source File Wizard to create CNT10
  component.

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2.5 Creating the CNT10 module

• Add the in direction type ports
• (STD_LOGIC)
• CLK
• ENABLE
• RESET
• Add the out direction type ports
  (STD_LOGIC_VECTOR)
• COUNT30
• (STD_LOGIC)
• COUT

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2.6 Creating the CNT10 module

• Add SYNOPSYS library declaration (before the
  entity declaration)
• The CNT10 architecture may look as in following
  picture

library SYNOPSYS use SYNOPSYS.STD_LOGIC_ARITH.a
ll
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2.7 Creating the CNT10 module
architecture cnt10 of cnt10 is signal
COUNTER INTEGER range 0 to 9 begin process
(CLK, RESET) begin if RESET'1' then
COUNTER lt 0 COUT lt '0' elsif CLK'1'
and CLK'event then COUT lt '0' if
ENABLE '1' then if COUNTER 9 then
COUNTER lt 0 COUT lt '1'
else COUNTER lt COUNTER 1
end if end if end if end
process COUNT lt CONV_STD_LOGIC_VECTOR(COUNTER
,4) end cnt10

• The CNT10 architecture.

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2.8 Simulating the CNT10 module

• Save the CNT10.VHD file
• Close the CNT10.VHD file
• Drag it into the FUNCTIONAL subfolder
• Compile the CNT10.VHD file (select the CNT10.VHD
  item in the Design Browser and use the Compile
  option from the shortcut menu)
• Set the CNT10 (CNT10) entity-architecture pair as
  top-level unit for simulation

65
2.9 Simulating the CNT10 module

• Initialize the simulation (Simulation /
  Initialize Simulation option)
• Invoke the new Waveform Editor window - click on
  theicon
• Click on the Root cnt10 item and dragdrop
  signals into the Waveform Editor window

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2.10 Simulating the CNT10 module

• Enter the formula in the Console window and press
  Enter key
• force CLK 0 0, 1 10 ns -r 20 ns
• The above formula will generate the clock wave
  with the 20 ns period
• Enter the following formula to force the RESET
  signal
• force RESET 1 0, 0 25 ns
• This formula specifies the single 25 ns pulse
• Enter the last formula to force the ENABLE
  signal
• force ENABLE 0 0, 1 50 ns
• For more information about force command type
• help force

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2.11 CNT10 module description

• Adjust the simulation step to 100 ns (if
  necessary)
• Click the icon to progress the simulation
• After clicking three times on the icon
  the waveforms should look like this
• End simulation (Simulation / End Simulation
  option)
• Save the waveform into the file as CNT10.AWF

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2.12 Creating CNT_BCD module

• To complete the 4-decades counter create the new
  VHDL file
• Close all the documents and use the New Source
  File Wizard to create CNT_BCD component.

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2.13 Creating CNT_BCD module-ports

• Add the in direction ports (STD_LOGIC)
• CLK
• ENABLE
• RESET
• Add the out direction ports (STD_LOGIC_VECTOR)
• BCD_A30
• BCD_B30
• BCD_C30
• BCD_D30
• (STD_LOGIC)
• FULL

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2.14 Creating CNT_BCD module

• Use Copy Declaration option to insert the CNT10
  component declaration to CNT_BCD.VHD file (the
  Design Browser Files tab)

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2.15 Creating CNT_BCD module

• Paste the declaration into the CNT_BCD.VHD file
  (between architecture declaration and the begin
  keyword)

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2.16 Creating CNT_BCD module
library IEEE use IEEE.std_logic_1164.all entity
CNT_BCD is port ( CLK in STD_LOGIC
ENABLE in STD_LOGIC RESET in
STD_LOGIC BCD_A out STD_LOGIC_VECTOR (3
downto 0) BCD_B out STD_LOGIC_VECTOR (3
downto 0) BCD_C out STD_LOGIC_VECTOR (3
downto 0) BCD_D out STD_LOGIC_VECTOR (3
downto 0) FULL out STD_LOGIC ) end
CNT_BCD architecture CNT_BCD of CNT_BCD is --
Component declaration of the "cnt10(cnt10)"
unit -- File name contains "cnt10" entity
.\src\cnt10.vhd component cnt10 port( CLK
in std_logic RESET in std_logic ENABLE
in std_logic COUT out std_logic COUNT
out std_logic_vector(3 downto 0)) end
component for all cnt10 use entity
WORK.cnt10(cnt10) signal COUT_A, COUT_B,
COUT_C, COUT_D std_logic begin -- ltltenter
your statements heregtgt end CNT_BCD

• Add the internal signals declaration
• signal COUT_A, COUT_B,
• COUT_C, COUT_D std_logic

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2.17 Creating CNT_BCD module

• Add four instances of CNT10 component U10, U11,
  U12, U13
• Use conditional signal assignment to generate the
  FULL signalFULL lt '1' when (COUT_A'1' and
  COUT_B'1' and COUT_C'1' and COUT_D'1') else
  '0'
• The next slide shows the whole cnt_bcd.vhd code

-- ltltenter your statements heregtgt begin U10
cnt10 port map(CLK gt CLK, RESET gtRESET,
ENABLE gt ENABLE, COUT gt COUT_A, COUNTgtBCD_A)
U11 cnt10 port map(CLK gt COUT_A, RESET
gtRESET, ENABLE gt ENABLE, COUT gt COUT_B,
COUNTgtBCD_B) U12 cnt10 port map(CLK gt
COUT_B, RESET gtRESET, ENABLE gt ENABLE, COUT gt
COUT_C, COUNTgtBCD_C) U13 cnt10 port map(CLK
gt COUT_C, RESET gtRESET, ENABLE gt ENABLE, COUT
gt COUT_D, COUNTgtBCD_D) FULL lt '1' when
(COUT_A'1' and COUT_B'1' and COUT_C'1' and
COUT_D'1') else '0' end CNT_BCD
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library IEEE use IEEE.std_logic_1164.all entity
CNT_BCD is port ( CLK in STD_LOGIC
ENABLE in STD_LOGIC RESET in
STD_LOGIC BCD_A out STD_LOGIC_VECTOR (3
downto 0) BCD_B out STD_LOGIC_VECTOR (3
downto 0) BCD_C out STD_LOGIC_VECTOR (3
downto 0) BCD_D out STD_LOGIC_VECTOR (3
downto 0) FULL out STD_LOGIC ) end
CNT_BCD architecture CNT_BCD of CNT_BCD is --
Component declaration of the "cnt10(cnt10)"
unit -- File name contains "cnt10" entity
.\src\cnt10.vhd component cnt10 port( CLK in
std_logic RESET in std_logic ENABLE in
std_logic COUT out std_logic COUNT out
std_logic_vector(3 downto 0)) end
component for all cnt10 use entity
WORK.cnt10(cnt10) signal COUT_A, COUT_B,
COUT_C, COUT_D std_logic begin U10 cnt10
port map(CLK gt CLK, RESET gtRESET,
ENABLE gt ENABLE, COUT gt COUT_A, COUNTgtBCD_A)
U11 cnt10 port map(CLK gt COUT_A, RESET
gtRESET, ENABLE gt ENABLE, COUT gt COUT_B,
COUNTgtBCD_B) U12 cnt10 port map(CLK
gt COUT_B, RESET gtRESET, ENABLE gt ENABLE, COUT
gt COUT_C, COUNTgtBCD_C) U13 cnt10
port map(CLK gt COUT_C, RESET gtRESET, ENABLE gt
ENABLE, COUT gt COUT_D, COUNTgtBCD_D) FULL lt
'1' when (COUT_A'1' and COUT_B'1' and
COUT_C'1' and COUT_D'1') else '0' end CNT_BCD
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2.19 Creating CNT_BCD module

• Save the created code
• Close VHDL editor
• Drag the cnt_bcd.vhd item to the FUNCTIONAL
  folder
• Compile the cnt_bcd.vhd file

76
3.1 Simulating using the Waveform

• This section will show the following operations
• How to set top-level design entity
• How to initialize simulation
• How to simulate the tested unit
• How to work with the waveform window

77
3.2 Top Level Selection

• Set the top-level entity-architecture pair
  (CNT_BCD-CNT_BCD).
• Initialize simulation (Simulation/Initialize menu
  option).

78
3.3 Using Design Browser

• Go to the Structure tab of Design Browser and
  click on the RootCNT_BCD item
• Select all the counter ports (click on the BCD_A
  item, depress the Shift key and click on the
  RESET item)

79
3.4 Adding Signals to Waveform

• Invoke the pop-up menu and choose Add to Waveform
  option.
• You can also dragdrop them into the waveform
  window

80
3.5 Using stimulators

• Select CLK signal on the waveform and invoke its
  shortcut menu.

81
3.6 Clock Stimulator

• Choose Stimulators option and select Clock
  stimulator type for CLK signal
• Click on the Apply button

82
3.7 Hotkey Stimulator

• Do not close the Stimulators dialog in the
  waveform window select the ENABLE signal - it
  will appear in the Signals list of stimulators
  window
• Select the Hotkey stimulator type click on the
  Press new hotkey field and press the E key
• Click on the Apply button

83
3.8 Formula Stimulator

• Select RESET signal select the Formula
  stimulator enter the following formula
• Click on the Apply button and then on the Close
  button

0 0, 1 200 ns, 0 400 ns
84
3.9 Formula format

• value time , value time ... -r
  period
• The default time unit is ps
• Examples
• 0 0, 1 10, 0 20 defines a 1-state pulse
  that starts at 10 (ps) and ends at 20
• 1 0, 0 5 ns -r 20 ns defines a pulse wave
  with period of 20 ns and 25 duty cycle
• 0000 0, 21000 1, 164 2 ps defines 4-bit
  aggregate wave "0000" at 0 ps, "1000" at 1 ps
  and "0100" at 2

85
3.10 Running Simulation

• Adjust the simulation step to 50 ns
• Perform Run For 50ns operation twice and hit E
  hotkey at simulation time 100ns to toggle signal
  value from logical 0 to 1.
• Perform Run Until 200ns (Simulation/Run Until
  menu option) and then toggle ENABLE signal back
  to 0, Run Until 600ns and then toggle to 1,
  Run Until 1200us to see the entire simulation
  results.

86
3.11 Running Simulation

• Observe when the counter starts counting. (650ns)
• Observe when the FULL pulse appears (FULL1).
• Stop simulation (Simulation/End Simulation menu
  option).

87
3.12 Custom Stimulators

• Replace Hotkey Stimulator Type with Custom Type.
  Click on the Apply button and then the Close
  button.
• Custom Stimulator will use existing waveform as
  simulation input.

88
3.13 Bus Display Radix

• Change BCD_A signal display radix select the
  signal and invoke the pop-up menu. Choose
  Properties option and Binary radio-button.
• Close the waveform and save it as BCD_CNT.AWF

89
3.14 Other Waveform Features

• Some additional waveform window features are
  available during simulation
• Edit Mode (you can drag signal events to change
  its shape)
• Measurement Mode (to measure distance between
  specific points of timing)
• Zoom Mode (zooming of timing)
• Stretch option (you can select waveform signals
  and stretch their timing)
• Bookmarks operations
• Signal sorting

90
4.1 Simple debugging features

• This section will demonstrate the following
  operations
• How to work with Breakpoints
• How to work with Watch window
• How to Trace the execution of the code

91
4.2 Setting up debug session

• Open previously saved BCD_CNT.AWF waveform file.
  Use Resources tab of the Design Browser. Double
  click on the bcd_cnt.awf item to open the
  waveform
• Make sure the top-level entity-architecture pair
  is set to CNT_BCD - CNT_BCD.

92
4.3 Setting Breakpoints

• Open the CNT10.VHD file
• Place the breakpoint in the CNT10.VHD file (press
  the F9 key) on the following line
• Initialize simulation (Simulation/Initialize
  Simulation menu option).
• Open Watch window (View/Watch menu option).

COUNTER lt COUNTER 1
93
4.4 Setting up the Watch window

• Click on the U10cnt10 item in the Design Browser
  Structure tab.
• Using drag and drop feature, add to the Watch
  window the COUT and COUNTER signals

94
4.5 Watch Display Radix

• To change the display radix in Watch window,
  select any signal and invoke the pop-up menu.
  Choose Display Radix option and choose e.g.
  Binary for Vectors and Numbers

95
4.6 Running Debug Simulation

• Perform Run operation (Simulation/Run menu
  option) several times and observe signal values
  in the Watch window.

96
4.7 Additional Debug Operations

• Trace Into, Trace Over, Trace Out modes are
  available during debugging process. Click Trace
  Into (F7) button several times to see the
  execution of the process.
• Perform Run operation (Simulation/Run menu
  option) several times and observe signal values
  in Watch window.
• There is a possibility to change variable value
  during simulation by editing it in Watch window.
• Before continuing end the simulation clear the
  breakpoint(s) (Simulation / Clear All Breakpoints
  option) and close all the windows

97
5.1 Using Test Bench Wizard

• This section will show the following operations
• How to use Test Bench Wizard
• How to create Single process test bench type
• How to verify automatically the tested unit

98
5.2 Using Test Bench Wizard

• Using test benches you can automatically verify
  your design.
• In this chapter, you will generate a Single
  Process test bench.
• The complete test bench file and some additional
  files will be generated automatically using
  Active-VHDL Test Bench Wizard.
• All stimulus driving inputs of the tested design
  will be taken from the previously saved waveform
  file. This way the stimulators and waveform
  signals will be converted into VHDL.

99
5.3 Test Bench Concept

• The figure below illustrates the concept of a
  test benchThe process implemented in
  the architecture body of a test bench forces
  desired stimulus on the inputs of the tested
  design unit (Unit Under Test UUT).

100
5.4 Using Test Bench Wizard

• Go to the Design Browser Files tab
• Make sure the top-level entity-architecture pair
  CNT_BCD - CNT_BCD is set.
• In Design Browser select CNT_BCD - CNT_BCD
  entity-architecture pair and invoke the pop-up
  menu. Choose Generate Test Bench option
• On the first screen of the wizard leave the
  default settings and click on the Next button.

101
5.5 Using Test Bench Wizard

• On the second screen of the wizard, check Test
  vectors from file box and Browse for BCD_CNT.AWF
  waveform file.
• Click on the Next button again on the Next
  button and finally on the Finish button

102
5.6 Using Test Bench Wizard

• The following files are created in TestBench
  folder
• CNT_BCD_TB.VHD - test bench file for tested
  BCD_CNT unit,
• CNT_BCD_TB_runtest.DO - the macro file for
  automatic compilation, simulation initialization,
  waveform creation and simulation
• Click CNT_BCD_TB_runtest.DO file and invoke the
  pop-up menu. Choose Execute option. Observe
  signals placed on new waveform.
• This way the entire simulation process was
  automated and fully contained in the VHDL source.

103
6.1 Creating and debugging FSM

• The FSM Editor is designed for behavioral
  description of synchronous State Machines.
• The CONTROL macro in FREQ_METER will be created
  as a state diagram.

104
6.2 Creating and debugging FSM

• Choose File / New / State Diagram option to
  invoke the New Source File Wizard
• Click on the Next button
• Enter the CONTROL filename
• Add the following ports
• Inputs (STD_LOGIC)
• CLK
• START
• RESET
• Outputs (STD_LOGIC)
• GATE
• END_MEASURE
• Click on the Finish button

105
6.3 Creating and debugging FSM

• In the control.asf invoke the shortcut menu for
  GATE output choose Properties and change the
  type to Registered
• Click on the Apply button select the END_MEASURE
  output and change its type to Registered

106
6.4 Creating and debugging FSM

• Select the CLK signal and check the Clock
  checkbox
• Click on the OK button

107
6.5 Creating and debugging FSM

• Invoke the shortcut menu for the state diagram
  (right-mouse-button click on the machine)
  choose CLK as a clock signal for the
  machine
• Click on the OK button

108
6.6 Creating and debugging FSM

• The CONTROL machine has 4 states
• IDLE - waiting for measurement start
• OPEN_GATE - enables the counter for one pattern
  clock cycle GATE lt 1
• CLOSE_GATE - disable the counter GATE lt 0
• END_CYCLE - resets the counter END_MEASURE lt 1

109
6.7 Creating and debugging FSM

• Click on the icon to add a state
• Place state on the diagram
• Invoke the shortcut menu for this state and
  change the name to Idle
• Click on the OK button

110
6.8 Creating and debugging FSM

• Click on the icon to add the reset
• End the reset transition on the Idle state
• Click on the icon to add condition
• Click on the Reset-to-Idle transition and enter
  condition
• reset1

111
6.9 Creating and debugging FSM

• Invoke the Machine Properties window choose the
  Reset tab and set the Asynchronous reset
  type
• Click on the OK button

112
6.10 Creating and debugging FSM

• Click on the icon to add entry action
• GATE lt 0
• END_MEASURElt1
• Add the OPEN_GATE state
• Click on the icon to add transition
  IDLE-to-OPEN_GATE

113
6.11 Creating and debugging FSM

• Click on the icon to add condition
• START1
• Add Entry Actions (the icon)
• GATE lt '1'
• END_MEASURE lt '0'

114
6.12 Creating and debugging FSM

• Complete the diagram. Save as CONTROL.ASF into
  FUNCTIONAL folder.
• Generate VHDL Code from the diagram and compile
  the file. (F11)

115
6.13 Simulating CONTROL FSM

• To simulate CONTROL FSM diagram, create a
  waveform using an Edit Mode. Invoke a new
  Waveform window ( icon).
• The simulator should not be initialized.
• Turn on the Edit Mode ( icon).
• Click on the Click here to add new signal add
  CLK, RESET, START signals.

116
6.14 Creating new waveforms

• Click at 350 us and drag to 0 ps to select an
  area to be filled.
• Choose the Fill option from the pop-up menu.

117
6.15 Filling out clock waveform

• Select Clock and enter 50 us period. Click OK
  button.

118
6.16 Filling out Reset Formula

• In the similar way fill the RESET signal with
  formula

119
6.17 Manual editing of START waveform

• Select the START signal from 350 us to 0 ps
• Press 0 key. The signal is now filled with 0
  value
• Select an area on START signal between 32 us and
  230 us
• Press 1 key. The selected area is filled with 1
  value.You can drag edges to the desired
  position.
• Click the right mouse button on Name header and
  choose Mode column.

120
6.18 Setting signal I/O modes

• By double clicking the port icons in the Mode
  column choose in mode for each signal.

121
6.19 Completing and saving waveforms

• Click the icon to turn off the Edit Mode.
• You should have a waveform like this
• Save the waveform as CONTROL.AWF and close the
  file.

122
6.20 Creating testbench from waveform

• Generate a testbench for control (control_arch)
  entity.
• Choose Single Process test bench type.
• Select CONTROL.AWF waveform file (check the Test
  vectors from file box).
• CONTROL_TB.vhd and CONTROL_TB_runtest.do
  files will be generated.
• Execute CONTROL_TB_runtest.do macro.The
  simulation results appear in the new waveform.
• Restart the simulation.

123
6.21 Initialize FSM for debugging

• Double click on the Sreg0_machine
  process.The CONTROL state diagram
  appears.
• Click the Trace Over Transition icon.

124
6.22 Highlighting states

• The current state is yellow

125
6.23 Debugging generated code

• Click the icon several times.
• Restart the simulation.
• Click the Trace Over icon several
  times.The state diagram is the source code for
  debug.
• Choose the Tools/Preferences option to change the
  code for debug.

• Change the Trace source code in (for State
  machine) to Generated VHDL code.

126
6.24 Setting breakpoints in FSM

• Click the Trace Over icon several
  times.The generated code from the state diagram
  is traced now.
• Restart the simulation. Double click on the
  Sreg0_machine process. Set a breakpoint on IDLE
  state.

127
6.25 Stopping at FSM breakpoint

• Click the icon. The simulation stops at
  the breakpoint
• Select again Breakpoint option to remove the
  breakpoint from the IDLE state.

Stopped at breakpoint on signal "/UUT/Sreg0"
(Value condition IDLE).
128
7.1 Creating top level schematic using Active-CAD

• This section shows how to create structural VHDL
  design with Active-CAD and how to verify the
  synthesis.
• The simulation of the entire design will be
  performed in Active-VHDL once the top level
  schematic is converted to VHDL.

129
7.2 Using Active-CAD schematic

• The structural VHDL code for the entire
  FREQ_METER design can be made using Active-CAD.
• The structure of the design can be drawn in
  Active-CAD schematic.
• The VHDL code will be automatically generated
  from the schematic editor.
• Active-CAD can also be used to verify VHDL macros
  with Metamor Synthesis Compiler.

130
7.3 Creating macro symbols in Active-CAD

• Create a new FREQM Active-CAD design.
• Copy the following files into the Active-CAD
  project folder
• cnt10.vhd
• cnt_bcd.vhd
• control.asf
• hex2led.vhd
• Use HDL Editor and open HEX2LED.VHDSet XVHDL as
  synthesis tool and then use Project / Create
  macro option.
• Use Active-CAD FSM Editor to create the CONTROL
  macro.
• Some macro symbols can be edited with Active-CAD
  Symbol Editor.

131
7.4 Creating macro symbols in Active-CAD

• Open the CNT_BCD.VHD file
• Choose the Synthesis / Options / Library Alias
  tab
• Click on the Add Alias button and add the work
  library
• Click on the Add File button and select the
  CNT10.VHD file
• Click on the OK button
• Create the CNT_BCD macro (Project / Create macro
  option)
• Create the top-level schematic

132
7.5 Adding links to Active-CAD files

• When FREQM schematic is finished, use Export
  Netlist option in Schematic Editor and perform
  Export VHDL netlist operation.
• The freqm.vhd file is the exported schematic VHDL
  netlist

133
7.6 Adding links to Active-CAD files

• To work back in Active-VHDL, you have to add to
  FUNCTIONAL folder source files from Active-CAD
  design directory. Check Make local copy checkbox.
• If you want to work simultaneously on in
  Active-CAD and Active-VHDL you have to add to
  Active-VHDL design source files located in
  Active-CAD design directory as shortcuts - to do
  this, uncheck Make local copy checkbox.

134
7.7 Simulating the entire design

• Add the exported top-level file freqm.vhd file to
  the Active-VHDL project and move it to the
  FUNCTIONAL folder. Compile all files in the
  FUNCTIONAL folder.
• Set the top level entity-architecture (FREQM -
  SCHEMATIC), initialize simulation and add signals
  to new waveform window.
• Assign the following stimulators
• F_INPUT - CLOCK 5 MHz
• F_PATTERN - CLOCK 20 kHz
• RESET - FORMULA 1 0, 0 8 us
• START - FORMULA 0 0, 1 32 us, 0 230 us
• Double check all clock frequencies placed as
  stimulators saved waveform file will be used for
  real timing simulation.

135
7.8 Converting waveform to test bench

• Simulate the entire design for 350 us
• Save the waveform as TOP_FUNCTIONAL.AWF.
• Use Generate Test Bench pop-up menu option for
  selected FREQ_M-SCHEMATIC top-level
  entity-architecture.
• Follow the wizard suggestions. Check Generate box
  in the last screen to produce configuration file
  for timing simulation.

136
7.9 Running test bench of entire design

• The following files are created
• FREQ_M_TB.VHD
• FREQ_M_TB_TIM_CFG.VHD
• FREQ_M_TB_runtest.DO
• Execute the FREQ_M_TB_runtest.DO script file and
  observe the simulation results.

137
Active-VHDL

• Lab 2
• Training Guide

138
Lab 2 Outline

• 8. Implementing design with synthesis
• 9. Simulating after synthesis
• 10 . Implementing design in FPGA
• 11. Using SDF files
• 12. Simulating routed design
• 13. Using functional test bench for timing
  simulation
• 14. Analyzing timing simulation errors
• 15. Using WAVES test bench for timing
  verification
• 16. Using simulation scripts for batch simulation
• 17. Advanced debugging features
• 18. Updating a VHDL library
• 19. Creating a VHDL library

139
8.1 Implementing design with synthesis

• Synthesis will be made with VHDL Metamor
  Compiler.
• All VHDL files of FREQ_METER design will be
  synthsized together.
• The synthesis process is invoked by one command
  placed in the the macro file.
• The RUNEXE command is used for running external
  EXE tools.
• Synthesis option and input files for the Matamor
  Compiler are stored in the parameter file (PAR
  file).
• The Metamor Compiler is invoked together with the
  PAR file.
• Note for this slide contains the sample PAR file
  for FREQ_METER design.

140
8.2 Implementing design with synthesis

• Create macro file (synthesize.do) for running the
  synthesis process.
• Use the command for running Metamor VHDL Compiler
  synthesis shown below
• runexe -wait MMVHDL\aldcvhdl.exe _at_
  DSN\src\synthesis\synthesis.par
• MMVHDL - AVHDL global variable points to the
  Metamor Compiler path
• DSN - AVHDL variable points to the current
  design directory
• The -wait switch suspends macro executing until
  the process is finished.
• The control.vhd file generated from CONTROL State
  Diagram is located by default in GENERIC
  directory, before running the synthesis, copy
  control.vhd file to FUNCTIONAL folder.
• The synthesized EDIF netlist file is placed into
  the PLACE_ROUTE folder.
• Note contains synthesize.do macro.

141
9.1 Simulating design after synthesis

• Some VHDL synthesis tools generate the structural
  VHDL code equivalent to the synthesized EDIF
  netlist used as an input to the Place Route
  process.
• Such a structural VHDL code is used to
  simulation, so synthesis results can be verified.
• The Metamor VHDL Compiler does not generate
  structural VHDL.
• ALDEC provides a tool to convert EDIF netlist
  into the equivalent VHDL code for simulation.

142
9.2 Simulating design after synthesis

• To invoke EDIF to VHDL conversion tool, create
  new convert_edif.do macro in the SYNTHESIS
  folder.
• cd DSN\src\synthesis
• Run edf2vhd
• runexe -wait ALDEC\bin\edf2vhd.exe -v top.edn
  ALDEC\bin\edfmap.ini
• Add the top.vhd file to the SYNTHESIS folder and
  compile it.
• You can use test bench created for functional
  simulation.
• To do this, open the test bench file
  FREQ_M_TB.vhd and modify configuration
  declaration replace the architecture name with
  SYNTHESIS.
• use entity work.FREQ_M(synthesis)
• See slide notes.

143
9.3 Simulating design after synthesis

• Recompile the test bench file FREQM_TB.VHD.
• Initialize simulation for changed test bench
  configuration TESTBENCH_FOR_FREQM.
• Simulation result should be the same as
  functional simulation result.

144
10. Implementing design withplace route

• Place and Route process is based on Xilinx M1
  Software.
• PR process is executed in BATCH mode using
  runexe command and the DOS BATCH file type.
• The BATCH file starts Xilinx tools in the
  appriopriate sequence.
• The PR process produces BIT file using for chip
  programming and backannotated VHDL file for a
  timing simulation. The additional SDF file
  contains the actual timing generics values.
• Timing VHDL file and SDF file are placed into
  TIMING folder.
• The -wait switch is not used, PR process may
  take a long time.
• The BATCH and macro files for running Xilinx PR
  process are shown in the slide notes.

145
11.1 Using SDF file in the design

• Add top_tim.vhd and top_tim.sdf file to the
  TIMING folder.
• Compile the top_tim.vhd.
• To load SDF file into the simulator you should
  set VHDL entity and hierarchy region where
  generics from the SDF file will be loaded.
• The generics values stored in SDF file have three
  sets Average, Maximal and Minimal.

146
11.2 Using SDF file in the design

• The SDF file will be loaded into simulator during
  simulation initialization
• The SDF loader check if the set in the Design
  Settings window region match the region pointed
  in the SDF file.
• When the regions match in the console window the
  appropriate message will be displayed during
  simulation initialize
• Design Loading sdf file ".\src\timing\Top_tim.sd
  f" into region "/"
• KERNEL Main thread initiated.
• KERNEL Kernel process initialization phase.
• SDF 2107 generic(s) read from C\my
  designs\training\freq_meter_1_13\src\timing\Top_ti
  m.sdf
• SDF 2107 generics found while 2107 generics
  read
• KERNEL Kernel process initialization done.

147
11.3 Using SDF file in the design

• When the region set in the Design Setting does
  not exist in the simulated design (e.g. U1) the
  following message can be displayed
• Design Error Region "/u1" does not found
• When the region set in the Design Setting exist
  but there are no generics depicted in the SDF
  file, simulation initialization will be stoped.
  You can observe the following message
• SDF 5252 generic(s) read from d\my
  design\freq_meter_two\src\timing\top_tim.sdf
• SDF Error top_tim.sdf(28)Generic
  reset_ibuf_0/tipd_i not found
• SDF Error top_tim.sdf(29)Generic
  reset_ibuf_0/tpd_i_o not found
• Fatal error occurred during simulation
  initialization.

148
11.4 Using SDF file in the design

• How to see loaded generics value ?
• In the Design Browser window select component for
  which you want to see generics - e.g. FULL_OBUF
  X_BUF
• In the lower window generics are shown with the
  G prefix
• The generics read from SDF file are
• tipd_I and tpd_I_O
• In the SDF file find the records for selected
  objects.
• In the slide notes appropriate piece of SDF file
  is shown.

149
12. Simulating routed design

• Waveforms created during functional simulation
  can be used to simulate timing version of the
  design, this is the easiest way.
• For timing simulation, functional test bench can
  be used.
• The WAVES test bench can also be used for timing
  simulation.
• The following slides demonstrates using above
  possibilities.

150
13. Using functional test bench for timing
simulation

• To use a functional test bench you have to modify
  the timing configuration file created during test
  bench generation.
• Modify the 21st line in FREQ_M_TB_tim_cfg.vhd
  file as follows
• use entity work.FREQM (STRUCTURE)
• Compile modified configuration file.
• Set region to loading SDF file properly.

151
14.1 Analyzing timing simulation errors

• Timing simulation process is much longer then the
  functional one.
• Vital Glitches warningsThey denotes fact that
  pulse observed on input port of element is
  shorter than propagation time of this element.
  Such a pulse will not propagate through a
  component.
• In most cases these warnings are harmless and
  any changes in the project are not required.
• Timing violations. The most frequent are
• Setup violations
• HOLD violations
• PULSE WIDTH violations
• In most cases too large clock frequency causes
  timing violations.

152
14.2 Analyzing timing simulation errors

• The timing violation warnings shouldnt appear
  and the designer has to be aware about their
  reason
• Using the Waveform Editor simplifies the timing
  debugging of the design.
• Before you start analyze timing violation try
  reduce frequency of clock signals
• If you want to keep dependence between clocks and
  another inputs use the STRETCH option in the
  Waveform Editor
• Using STRETCH for clocks and all input signals
  expands your waveform proportionally
• Sometimes HOLD violations appear in the
  synthesized part of the design

153
14.3 Analyzing timing simulation errors

• Initialize the timing simulation FREQM(STRUCTURE)
  as top-level unit. The SDF file should be loaded.
• Find the /RESET_IBUF_0 instance (X_BUF - a simple
  buffer) and add signals I, O, I_ipd to the new
  waveform window.

154
14.4 Timing generics

• Observe the timing generics value for this
  instance

• tipd_I1.5 ns(delay from port I to internal
  signal I_ipd)
• tpd_I_O3 ns (delay from I_ipd signal to O port)

155
14.5 VitalGlitch warnings

• Force the RESET signal with the command
• force RESET 0 0, 1 10 ns, 0 11 ns
• Perform the simulation for 15 ns (use the
  command)
• run 15 ns
• The following warning is issued

WARNING VitalGlitch GLITCH Detected on port O
Preempted Future Value 1 _at_ 14.5 ns Newly
Scheduled Value 0 _at_ 15.5 ns Time 12500 ps,
Iteration 0, Instance /reset_ibuf_0
156
14.6 VitalGlitch warnings

• Observe the signals in the waveformThere
  is a single pulse on the I port. The pulse width
• PW1 ns
• The internal I_ipd signal is delayed by
  Tipd_I1.5 ns

157
14.7 VitalGlitch warnings

• The raising edge on the I_ipd signal schedules a
  change ( 0 to 1) on the O signal after t_pd_I_O3
  ns11.5 ns 3 ns 14.5 ns This value
  is called Preempted Future Value Preempted
  Future Value 1 _at_ 14.5 ns

158
14.8 VitalGlitch warnings

• The falling edge on the I_ipd signal schedules a
  change (this time 1 to 0) on the O signal after
  tpd_I_O3 ns 12.5 ns 3 ns 15.5 ns
  This value is called Newly Scheduled Value
• Newly Scheduled Value 0 _at_ 15.5 ns

159
14.9 VitalGlitch warnings

• Because
• Newly Scheduled Value - Preempted Future Value
  1 ns
• 1 ns lt tpd_I_O3 ns
• the output O signal remains unchanged. The
  tpd_I_O is an inertial delay which means that a
  pulse shorter than tpd_I_O value will not be
  propagated.The information about this analyzing
  appears in the Console as a VitalGlitch warning

WARNING VitalGlitch GLITCH Detected on port O
Preempted Future Value 1 _at_ 14.5 ns Newly
Scheduled Value 0 _at_ 15.5 ns Time 12500 ps,
Iteration 0, Instance /reset_ibuf_0
160
14.10 Timing violations

• Restart the simulation - the SDF file should be
  loaded
• To simulate timing violations force the F_INPUT
  signal with the formula
• force F_INPUT 0 0, 1 10 ns, 0 14 ns
• The above formula generates a single 4 ns pulse

161
14.11 Timing violations

• Locate the /BCD_T_1_DFF_OUT_FFY instance of X_FF
  flip-flop

• Observe that the min. pulse width on the CLK
  input is tpw_CLK_negedge4.5 nsand
  tpw_CLK_posedge4.5 ns

162
14.12 Timing violations

• Add CLK and CLK_ipd signals (dragdrop from
  Design Browser) to the new waveform and run
  simulation for 19 ns

163
14.13 Timing violations

• Notice the message in the Console
  windowIt means that the pulse on the CLK
  input is too short (4 ns) while the expected
  value is 4.5 ns (or greater)

WARNING /X_FF PULSE WIDTH High VIOLATION ON
CLK Expected 4.5 ns Observed 4 ns At
18.102 ns Time 18102 ps, Iteration 0,
Instance /bcd_t_1_dff_out_ffy
164
15.1 Using WAVES test bench for timing simulation

• The WAVES-based test bench simultaneously drives
  the inputs and compares the output response with
  a previously saved pattern.
• During simulation the test vectors (stimulus and
  output response) are taken from the test vector
  file (.VEC).
• The Test Bench Wizard generates the test vector
  file (.VEC) from a waveform file (.AWF) created
  with Waveform Editor.
• The typical way is to use WAVES test bench is to
  create test bench on early design stage and use
  it during design developing.
• The second possibility is to use WAVES test bench
  to compare timing and functional simulation
  results.
• The WAVES test bench is compliant with IEEE
  Standard and can be use also in electrical test
  environment.

165
15.2 Using WAVES test bench for timing simulation

• The waveform file created during functional
  simulation will be used as test vectors in WAVES
  test bench.
• Set entity FREQM (STRUCTURE) asa top level and
  invoke Test Bench WIZARDt select WAVES based
  type.
• Broswe for the functional waveform file
  top_functional.awf.
• Follow WIZARD suggestions, do not modify
  anything.

166
15.3 Using WAVES test bench for timing simulation

• The WAVES test bench WIZARD creates several files
  placed by default in WAVES folder.

• FREQ_M_TB_pins.vhd - package contains declaration
  of enumerated type with the UUT ports names
• FREQ_M_TB_declaration.vhd - package contains
  declaration of all used in test bench constants
  and types
• FREQ_M_TB_header - TEXT header file contains the
  main information about WAVES test bench files and
  objects
• waves_objects.vhd - standard WAVES package
• waves_utilities.vhd - package contains procedures
  for monitoring and comparison the UUT outputs
• waves_generator.vhd - package contains procedure
  for reading test vectors from the file and
  generating stimulus and output patterns
• top_functional.vec - file with test vectors
• FREQ_M_TB.vhd - top level test bench entity
• FREQ_M_TB_runtest.do - macro for running
  compilation files, initialization simulation,
  waveform creating and simulation the whole test
  bench
• The shortcut icon denotes that file is
  located outside design directory
• Files with shortcut icon are not generated by the
  WIZARD

167
15.4 Using WAVES test bench for timing simulation

• File with icon arent generated by WIZARD
  these files are constant and are the same for
  each WAVES test bench
• The rest of files are specific for the design
• For the user two of