Evaluation of Code Compression Method for Low Power System

1
Evaluation of Code Compression Method for Low
Power System

• Shin Jin Ah
• Parallel Processing Lab.
• Information Communications University

2
Contents

• Overview of Code Compression
• Previous Works
• Evaluation
• Result
• References

3
Code Compression(1)

• Code compression
• Power consumption
• Reducing the bandwidth for the I/O interface
• Occupied area of memory
• Size
• Decreasing memory size gt Decreasing die area
• Cost
• Reducing the cost for the smaller die area

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Code Compression(2)

• What is compressed?
• A program generally use only small part of a
  given instruction set.
• There are much repetition of instructions in the
  program.
• Embedded System Assumption
• The size of each program which runs on the
  processor is relatively small.
• Additional circuits can be easily integrated into
  a chip.

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Code Compression(3)

• Disadvantages
• Decompression time
• Longer time consumption
• More power consumption
• Necessary area for dictionary table segment
• Decompressor maintain dictionary table(transform
  table)
• There are few duplication instruction

6
Previous Works

• Huffman code
• Wolfe
• Arauju
• CodePack
• IBM PowerPC code compression system
• ARM Thumb

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Evaluation(1)

• Base Architecture
• SE3208 32-bit microprocessor
• 8 32-bits general purpose register
• 7 special purpose register
• No cache memory
• 16-bit instruction set
• ELF binary execution file format
• No modification of instruction set architecture
• Using dictionary compression
• Add the compression function(S/W)
• Add the decompression module(H/W)

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Evaluation(2)

• SE3208 ISA Compression Concept
• text segment index segment

16bits
log2 n bits
16bits
3 4 5 3 4 4
leri 0x0 leri 0x53F ldi 0x53FE, r2
leri 0x0 leri 0x53F leri 0x53F
leri 0x0 leri 0x53F ldi 0x53FE, r2
n
. . .
. . .
dictionary segment
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Evaluation(3)

• Metric
• Compression ratio

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Result(1)

• Size of compressed program
• dictionary segment size
• index segment size ( of instructions ? log2n)
  
• Average compressed ratio 75.91
• Limitation of 16 bit instruction set

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Result(2)

• Compare the instruction number

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Result(3)

• Compression Ratio

13
References(1)

• 1 C. Lefugy, E. Piccininni, and T. Mudge,
  "Evaluation of a High Performance Code
  Compression Method," IEEE 32nd Annual
  International Symposium on Microarchitecture
  (Micro-32), 1999.
• 2 A. Wolfe and A. Chanin, Executing Compressed
  Programs on An Embedded RISC Architecture, in
  proc. Micro-25 The 25th Annual International
  Symposium on Microarchitecture, 1992.
• 3IBM, CodePack Compression system Code
  Compression for PowerPC Processors 1998
• 4 M. Kozuch and A. Wolfe, Compression of
  Embedded System Programs, IEEE International
  Conference on Computer Design, 1994.
• 5 D. Burger and Todd M. Austin, The
  SimpleScalar Tool Set, version2.0

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References(2)

• 6 C. Lefugy, E. Piccininni, and T. Mudge,
  Reducing Code Size with Run-time
  DecompressionHigh-Performance Computer
  Architecture, 2000. HPCA-6. Proceedings. Sixth
  International Symposium on, 1999. pp.219-228
• 7 G. Araujo, P. Centoducatte, M. Cortes, and
  Ricardo Pannain, Code Compression Based on
  Operand Factorixation, Proc. 31st Ann.
  International Symp. On Microarchitecture, 1998.
• 8 Yanbing Li, Henkel, k. A Framework for
  Estimatin and Minimizing Energy Dissipation of
  Embedded HW/SW Systems,Design Automation
  Conference, 1998. Proceedings , 1998 , pp.188
  -193
• 9 Y. Yoshida, B. Song, and H. Ohuhata
  Low-Power Consumption Architecture for Embedded
  Processor, ASIC, 1996., 2nd International
  Conference on , 1996 , pp. 77 -80