Camera Auto Focus

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Camera Auto Focus
Final Presentation, April 30th, 2007
Project Objective Design a low-power, small
autofocus chip for use in camera or other
hand-held device

• Group W1
• Tom Goff
• Dave Hwang
• Kate Killfoile
• Greg Look
• Design Manager Bowei Gai

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Agenda

1. Market
2. Algorithm
3. Architecture
4. Verification
5. Layout
6. Conclusion and questions

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The Market
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Target market

• Camera manufacturers
• Digital
• Video
• Security
• 82 million cameras expected to be sold in 2007
• 18 billion industry

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Autofocus methods
Active
Passive
Analyze image
Focus
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Passive vs. active
Pros Cons
Active Able to focus in the dark Focus with little contrast High power Fooled by reflection and interference Limited range
Passive Faster and more accurate Bigger range Less power Hard to fool Cannot focus in the dark High contrast needed
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Where our chip fits in
Our Chip
18-525 Implementation
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Why hardware?

• Software solutions are slow
• Software rule logic uses memory
• Less room for pictures!
• Software computation draws power
• Shorter battery life

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Why our chip?

• Adaptability to any camera and lens
• No calibration methods needed
• Large market
• Most commercial digital cameras use passive focus
• Customizable
• Rule values can be adjusted

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Current industry

• Size
• 10 mm x 10mm x 5 mm dimensions
• Power
• 5 mW minimum industry standard
• Speed
• Only need to be faster than motor
• High end digital cameras 60 fps
• High end video camera 3000 fps
• Speed floor at 3 kHz

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Design goals

• Size Goal 100,000 um2
• Power Goal lt 5 mW
• Speed Goal 100 kHz

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Our Algorithm
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Our algorithm

• 2 main inputs to our chip

di change in sharpness
ag Average grey level
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Our algorithm
weighted constant
match
Rule 1
weighted constant
ag
match
Rule 2
Range of di and ag
di
weighted constant
match
Rule 6
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Translation to hardware

• Floating point multiplier and adder
• Series of summed products
• Internal floating point format
• Only used 1 multiplier and adder
• Benefit reduced size
• Cost reduced speed
• Low power components
• Low power full adder
• Pass logic

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Architecture
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System architecture
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Floorplan evolution
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Signal flow
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SERF full adder

• 10 transistors
• Proven low-power design
• Weak output in some cases

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Carry-save multiplier

• Fewer full adders
• Compact design (0.437 density)
• Speed not an issue

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Floating point adder

• Handles de-normalized numbers
• Does not round
• Determines leading zeroes with combinational logic

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Floating point adder
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Floating point multiplier

• Reuses some submodules from the adder
• Three inputs means savings on exponent
  combination and normalization logic

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Floating point multiplier
Norm 2
Norm 1
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Verification
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Verification procedure
C implementation
Verilog
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Exhaustive testing

• Compared C implementation with Verilog

0.000724 error rate!
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Layout verification

• Hierarchical testing of modules
• Compared against expected schematic output
• Edge cases
• Generic cases

ag
di
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Layout
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Layer masks
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Specifications
Inputs Inputs
di 10 bit
ag 8 bit
enable 1 bit
reset 1 bit
clk 1 bit
Outputs Outputs
motor_out 10 bit
Area 206 x 187 38,689 µm2
of transistors pmos 4,948 nmos 5,846 Total 10,794
Density 0.279
Aspect ratio 1.099
Clock speed 666 MHz
Throughput 10 MHz (max speed)
Power 0.977 mW
33 pins total
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Conclusion

• Advise caution with shared libraries
• Floor planning is super important
• Test, test, and more test at every stage
• Solve problems early

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Questions?
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Global simulation
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ag simulation
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di simulation