Status

1
Status
BWRC Summer Retreat 2004
Bob Brodersen Dept. of EECS Univ. of
Calif. Berkeley
2
Retreat Theme

• What should we do in the BWRC to maximize its
  impact?
• This leads to two questions
• Who are we trying to make an impact on?
• What kind of impact do we want to make?

3
3 Constituencies

• Academia Teaching and research
• Large Companies RD research
• Startups Transitioning research into products
• Past students are distributed (very) roughly as
• Academia 15
• Large companies 40
• Startups 45

4
Students and Staff

• 60 GHz
• Chinh Doan
• Sohrab Emami
• Patrick McElwee
• Brian Limketkai
• David Sobel
• Sayf Alalusi
• Cognitive and reconfigurable radios
• Danijela Cabric
• Tina Smilkstein
• Jing Yang
• Mubaraq Mishra
• Sue Mellers
• Ada Poon

• UWB
• Ian ODonnell
• Mike Chen
• Stanley Wang
• Design Flow BEE
• Brian Richards
• Chen Chang
• Changchun Shi
• Kevin Camera
• Hayden So
• Andrew Chang
• Johan Vanderhagen

5
Five Basic Application Areas

• 60 GHz CMOS Radio Design
• Ultra-wideband Radios
• Rapid Design Methodologies
• Cognitive Radios
• BEE2 FPGA computing platform

6
60 GHz CMOS - Status

• Ali Niknejad and David Sobel will report on this
  effort
• Key results
• Circuits have been fabricated and tested and are
  amazingly close to predictions (within a fraction
  of a dB over 10s of GHz of bandwidth)
• We have shown that 130 nm CMOS can be used up to
  60 GHz

7
RF Phase Shifter Architecture

• 1 data stream, RF phase shifters only, digitally
  controlled
• Achieves high antenna gain in an arbitrary
  direction
• Low hardware complexity N RF phase shifters
• Low system power consumption

r(t)
s(t)
a0
a0
a1
a1
S
a2
a2
8
Phase shifter Test Chip April 04

• Common Gate / Switches
• Common Source (Buffers)
• Big devices
• (W/L 100um/0.13um)
• Small devices
• (W/L 20um/0.13um
• Test and calibration
• structures
• The S-parameters of these
• devices were extracted and
• are being used to design a
• new chip with a 4-way array
• of phase shifters.
• Packaging is still an issue.

9
Five Basic Application Areas

• 60 GHz CMOS Radio Design
• Ultra-wideband Radios
• Rapid Design Methodologies
• Cognitive Radios
• BEE2 FPGA computing platform

10
UWB - Status

• Design is completed for a ultra low power
  impulse based transceiver layout is in final
  stages
• Test chip back on 0-1 GHz LNA
• Spatial channel measurements over 0-6 GHz band
• Architecture for low power 2 GHz, 7 bit, A/D
  defined
• Algorithms developed for object tracking and
  imaging (Anant Sahai will report on this)

11
Sub-sampled analytic UWB Radio

• Goal An ultra low-cost UWB radio
• Subsampling to remove local oscillator and mixer
  and reduce requirements on A/D.
• Analytical signal processing to ease timing
  recovery without oversampling and interpolation.

12
LNA Schematic and Simulation
Av
NF
dB
s11
Frequency(MHz)

• Common Gate/Common Source shared current
  architecture

• Power 0.61mW
• Area 475um x 570um

13
UWB LNA Test Chip

• ST Microelectronics 0.13um CMOS process w/ MIM
  cap
• LNAs w/ and w/o back-gate coupling
• Buffer for de-embedding
• Single-ended LNA for probe station tests

LNA w/ buffer (no back-gate coupling)
Buffer
4mm
s21
Single-ended LNA
s11
LNA w/ buffer
dB
s22
s12
2mm
On-chip single-ended probing results
14
Five Basic Application Areas

• Millimeter Wave CMOS Design
• Ultra-wideband Radios
• Rapid Design Methodologies
• Cognitive Radios
• BEE2 Real time computing platform

15
Five Basic Application Areas

• 60 GHz CMOS Radio Design
• Ultra-wideband Radios
• Rapid Design Methodologies
• Cognitive Radios
• BEE2 FPGA computing platform

16
Rapid Design Methodologies

• Automated Digital design Insecta flow
• Simulink/Stateflow to layout in use
• Evolving to new tools, new technologies basic
  infrastructure
• Automated Analog Design
• Layout operational
• Pipeline converter sized using non convex
  optimization
• Large scale system design application Multiple
  antenna processing (SVD consideration for
  802.16)

17
Design Flow

• Minimize energy-area cost under throughput
  constraint
• Use Xilinx block-based macros with optimal
  parallelism / time-mux
• Basic add/sub, mult, div, 1/sqrt
• More complex vector mult, norm

MIMO Algorithm (Equations)
Behavioral Model (Simulink)
Structural Model (Simulink/Xilinx blocks)
Wordlength optimization (in-house FFC tool)
BEE Emulation
ASIC
18
Large Scale System Design ( 64 channel, 4x4 SVD)
Consumes approx. 2/3 of BEE
19
Result of a top-level floating to fixed point
optimization
12,8
10,8
14,9
12,11
12,8
12,9
12,8
8,5
12,9
10,8
20
Five Basic Application Areas

• 60 GHz CMOS Radio Design
• Ultra-wideband Radios
• Rapid Design Methodologies
• Cognitive Radios
• BEE2 FPGA computing platform

21
The spectrum shortage.

• All frequency bands up to 60 GHz (and beyond)
  have FCC allocations for multiple users
• The allocation from 3-6 GHz is typical - seems
  very crowded.

22
The reality
The TV band
0 1 2 3
4 5 6 GHz

• Even though the spectra is allocated it is almost
  unused
• Cognitive radios would allow unlicensed users to
  share the spectrum with primary users
• The TV band is interesting, but higher
  frequencies are even more attractive

23
Cognitive Radios - Status

• FCC continues to move forward on releasing
  spectra, probably 50 Mhz around 3.5 GHz and 275
  MHz in 400-700 MHz
• Working on both PHY and MAC layers (with Adam
  Wolisz)
• Our approach is to develop a hardware platform
  based on BEE for algorithm and protocol
  investigation.
• Primarily interested in the 3-10 GHz band though
  looking at the TV band issues

24
We seek comments on our Whitepaper on our
Cognitive Radio system model (version 12.1)

• CORVUS
• A Cognitive Radio Approach for Usage of Virtual
  Unlicensed Spectrum
• Authors
• Prof. Robert W. Brodersen (UC Berkeley)
• Prof. Adam Wolisz (TU Berlin)
• Danijela Cabric (UC Berkeley)
• Shridhar Mubaraq Mishra (UC Berkeley)
• Daniel Willkomm (TU Berlin)

25
CORVUS will be prototyped on our BEE platform
Optical Riser Cards
Peripheral Device
RF Front-end
Xilinx Chip
BEE
Optical Transceivers
26
Five Basic Application Areas

• 60 GHz CMOS Radio Design
• Ultra-wideband Radios
• Rapid Design Methodologies
• Cognitive Radios
• BEE2 FPGA computing platform

27
BEE2 FPGA computing platform - Status

• Second Generation BEE, being built in conjunction
  with Xilinx
• Programmed from high level languages
  Simulink/Stateflow, Handel C,
• A model for future flexible radio
  implementations the right way to do software
  defined radios!
• Used for real time simulations of network
  protocols, physical layer algorithms, multiple
  antenna processing, etc
• Coordinating with the Radio Astronomy and SETI
  groups as a design driver (the ultimate Cognitive
  Radio!)

28
Basic Computing Element

• Single Xilinx Virtex 2 Pro 100 FPGA
• 100K logic cells
• 2 PowerPC405 cores
• 444 dedicated multipliers (18-bit)
• 1MB SRAM on-chip
• 20X 3.125-Gbit/s duplex serial communication
  links (MGTs)
• 4 physical DDR2-400 banks
• Each banks has 72 data bits with ECC
• Independently addressed with 16 banks total
• Up to 12.8 GBps memory bandwidth, with maximum 8
  GB per FPGA capacity
• Up to 4 Byte/FLOP

29
Compute Node

• 4 computing elements 1 control element
• 2D mesh connection between computing nodes
• 104 bit _at_ 200MHz DDR
• 41.6 Gbps per link
• Star connection from control node to computing
  nodes
• 48 bit 200 MHZ DDR
• 19.2 Gbps per link

30
Example for comparison Dynamic programming task

• Sequence comparison expressed in terms of a 2D
  dynamic programming graph
• Every possible alignment of the 2 sequences are
  represented
• For Large Sequences complete search of graph is
  too slow
• BLAST is a heuristic which localize the search to
  only the areas of the graph where there is a
  complete match of length K
• Default K value
• 11 for DNA
• 3 for Proteins

31
Performance Comparison toGreen Destiny Cluster
(128 nodes)

• 4 FPGA single BEE2 node vs. 128 Transmeta 667MHz
  TM5600
• BEE2 10 times faster
• About 100 times better price/performance ratio

32
Performance Comparison toTimeLogic Hardware
Accelerator

• 4 FPGA single BEE2 node vs. TimeLogic DeCypher 4
  modules (16 FPGA)
• 120 times faster on a single BEE2 module
• 2000 times better price/performance ratio

33
Summary

• Complex circuits at 60 GHz using 130 nm CMOS
  demonstrated next step complete transceiver
• UWB LNA tested, digital backend designed, final
  transceiver in layout, chip in fabrication by end
  of summer
• Multi-antenna system design underway with
  Insecta/BEE flow and power/area optimization
• Cognitive radio system model white paper and
  hardware prototyping platform design completed
• Next generation BEE (BEE2) designed and will be
  in fabrication this summer