An Ultra Low Power System Architecture for Sensor Network Applications

1
An Ultra Low Power System Architecture for Sensor
Network Applications

• Mark Hempstead, Nikhil Tripathi, Patrick Mauro,
  Prof. Gu-Yeon Wei, Prof. David Brooks
• Division of Engineering and Applied
  SciencesHarvard UniversityCambridge, MA

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Overview

• Wireless sensor networks (WSN) are constrained by
  energy consumption
• Goal Average power consumption lt100 µW enables
  energy scavenging methods
• Our architectural approach
• Holistic approach
• Event-driven architecture
• Modular hardware accelerators
• Fine-grain power management
• In the implementation phase

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Outline

• What are sensor networks?
• Project motivation and design constraints
• Event-driven architecture
• Performance and power estimates
• Conclusion and future work

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Sample Application Space

• Monitoring Apps
• Structural/Earthquake/Weather/Habitat monitoring
• Building/Border/Battlefield detection
• Road/traffic monitoring
• Medical Apps
• Long-term health monitoring
• Untethered Pulseox Sensors
• Business Applications
• Supply Chain Management
• Expired/Damaged Goods Tracking
• Automatic Checkout Systems

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Example App Great Duck Island

• Great Duck Island (GDI), Maine - (UC Berkeley)
• Gather temp, humidity, IR readings from Leach's
  Storm Petrel burrows and weather station motes
• Determine occupancy of nests to understand
  migration patterns
• Total of 150 nodes deployed in 2003, over 650,000
  observations taken
• Performance Requirements are Low
• Samples taken and transmitted once every 5 min
• Power consumption limited lifetime of deployment

Single Hop Network
Multi-Hop Network
R. Szewczyk et al. An Analysis of a Large Scale
Habitat Monitoring Application. ACM Conference on
Embedded Networked Sensor Systems (SenSys), 2004.
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Example Sensor Network Node
Wireless Communication and Adhoc Networking
Low PowerLow Throughput TinyOS for Event Driven
Programmable CPU
Battery Operated
Interface to Various Sensors
Small Form Factor
Mica2 Mote Designed by UC Berkeley,
Manufactured by Crossbow
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Energy is the primary limitation

• Mica2 Power Consumption Measured by component
• Not the complete picture, how is power consumed
  in an application?

V. Shnayder, M. Hempstead, B. Chen, G.
Werner-Allen, M. Welsh. Simulating the Power
Consumption of Large-Scale Sensor Network
Applications. (SenSys'04).
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Application-level Power Analysis
Total energy consumption per component of
Surge, a multi-hop routing application, run for
60 sec on the Mica2 mote.
Due to General Purpose architecture of
CPU Requires software overhead to run TinyOS
Can be decreased at application and protocol
levels however this requires more CPU computation
Design Goal Average Power consumption of lt 100
µW to enable energy scavenging methods. Where
should design energy be focused to decrease
energy consumption?
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Regular Application Behavior
Receive and Forward
Sense and Transmit
Abstract View
Example - GDI
Message Arrives
Timer Interrupt
Every 5 min
Decode Message
Burrow Occupancy - infrared - humidity
Collect Sensor Data
Search Routing Table
- Pack data in packet - Calculate checksum
Prepare Message
Resend Radio Message
Send Radio Message
- wait for acknowledgement
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Key goals of our architecture
General Purpose CPU
Remove Software Overhead
OUR SYSTEM
Flexibility/Programmability
Retain Programmability
ASIC
Energy Efficiency

• Event-driven computation
• Hardware accelerators for power-efficiency
• Exploit regular operations
• Optimize for sensor net workloads
• Modular design
• Fine-grain power management

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Abstract view of architecture
General Purpose Microcontroller
Radio Transceiver
Shared Memory
Event Processor
Sensors
Slave Blocks
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Detailed view of architecture

• Regular events mapped solely to EP and slaves
• Micro Controller included for irregular events
• Slaves provide application specific HW
• All resource usage is explicit

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Event Processor

• Interrupts invoke EP interrupt service routines
• 8 instructions
• 4 power control/control transfer
• 4 read/write/transfer data to devices

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App. Example Sense Transmit
System Initialization/Reprogram
Timer Interrupt
Micro Controller
Sensors
Radio
Collect Sensor Data
Addr/Data
Event Processor
Message Processor
System Bus
Interrupt
Power Ctrl
Prepare Message
Data Filter
SRAM
Timer
Send Radio Message
Configuration written to memory and timer
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Example Sense Transmit (2)
Timer Interrupt
Micro Controller
Sensors
Addr/Data
Radio
Collect Sensor Data
Addr/Data
Event Processor
Message Processor
System Bus
Interrupt
Prepare Message
Power Ctrl
Data Filter
SRAM
Send Radio Message
Timer
Pseudo Code lttimer intaddrgt SWITCHON
ltsensorgt SWITCHON ltmessage procgt TRANSFER
ltreading sizegt ltsensor addrgtltmessage proc
addrgt SWITCHOFF ltsensorgt WRITEI ltctrl_wrdgt
ltmessage procgt TERMINATE
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Example Sense Transmit (3)
Timer Interrupt
Micro Controller
Sensors
Addr/Data
Radio
Collect Sensor Data
Addr/Data
Event Processor
Message Processor
System Bus
Interrupt
Prepare Message
Power Ctrl
Data Filter
SRAM
Send Radio Message
Timer
Pseudo Code ltmessage proc mesg. ready
intaddrgt SWITCHON ltradiogt TRANSFER ltmesg sizegt
ltmessage procgt ltradiogt SWITCHOFF ltmessage
procgt WRITEI ltctrl_wrdgt ltradiogt TERMINATE
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Example Sense Transmit (4)
Timer Interrupt
Micro Controller
Sensors
Addr/Data
Radio
Collect Sensor Data
Addr/Data
Event Processor
Message Processor
System Bus
Interrupt
Prepare Message
Power Ctrl
Data Filter
SRAM
Send Radio Message
Timer
Pseudo Code ltradio, message sent
intaddrgt SWITCHOFF ltradiogt TERMINATE
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Example Sense Transmit (5)
Timer Interrupt
Micro Controller
Sensors
Addr/Data
Radio
Collect Sensor Data
Addr/Data
Event Processor
Message Processor
System Bus
Interrupt
Prepare Message
Power Ctrl
Data Filter
SRAM
Send Radio Message
Timer
System Idle
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Implementation

• Process technology study (see paper)
• Does Moores Law help us?
• Leakage power increasing concern
• Tradeoff active power and leakage power
• Architectural enables low power circuit
  techniques
• Fine-grain power management VDD gating
• Simple Circuit Implementation
• Synchronous design
• VDD roughly 2VT
• Performance Target 100 kHz
• Possible to use less common circuit design styles
  (subthreshold, asynchronous)

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Initial Results

• Developed performance model for system
  architecture in SystemC (8K lines of code)
• GP microcontroller, event processor, slave
  blocks, radio
• Power Model
• VHDL for Event Processor Key Blocks
• Custom design (SRAM, CAM)
• 0.25 µm Process Technology
• Workload Analysis and early comparison to other
  architectures included in the paper

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Performance Comparison
Roughly 10x cycle-reduction justifies 100KHz
clock speed
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Power estimates
Unknown blocks GP microcontroller, busses,
off-chip interfaces
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Conclusion/Future work

• Wireless Sensor Networks provide unique
  opportunities for low power, low throughput
  design
• Architecture meets design goals
• Less than 100 µW average power consumption
• Event Processor provides event handling in HW
• HW slaves provide application specific processing
  for regular tasks
• Fits sensor network application characteristics
• Implementation phase of first chip
• Stay Tuned!