Extending and Expanding Moores Law Challenges and Opportunities

1
Extending and Expanding Moores LawChallenges
and Opportunities

• Shekhar Borkar
• Intel Corp.
• Aug 29, 2006

2
Outline

• Todays challenge Power
• Evolution of Multieverywhere
• Whats beyond Multi?
• Future challenges variations and reliability
• Resiliency
• Summary

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Goal 10 TIPS by 2015
Pentium 4 Architecture
Pentium Pro Architecture
Pentium Architecture
486
386
286
8086
4
Power is the Challenge!
)
1400
2
SiO2 Lkg
10 mm Die
1200
SD Lkg
Active
1000
800
Power (W), Power Density (W/cm
600
400
200
0
90nm
65nm
45nm
32nm
22nm
16nm
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Near Term Solutions

• Move away from Frequency alone to deliver
  performance
• More on-die memory
• Multi-everywhere
• Multi-threading
• Chip level multi-processing
• Throughput oriented designs
• Valued performance by higher level of integration
• Monolithic Polylithic

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mArchitecture Techniques
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Multi-Core
Power
Power 1/4
4
Performance
Performance 1/2
3
2
2
1
1
1
1
4
4
Multi-Core Power efficient Better power and
thermal management
3
3
2
2
1
1
8
Sources of Variations
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Impact of Static Variations
Today
1.4
Frequency 30 Leakage Power 5-10X
30
1.3
1.2
130nm
Normalized Frequency
1.1
1.0
5X
0.9
1
2
3
4
5
Normalized Leakage (Isb)
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Todays Freelance Layout
No layout restrictions
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Transistor Orientation Restrictions
Transistor orientation restricted to improve
manufacturing control
12
Transistor Width Quantization
Vdd
Vdd
Op
Ip
Op
Vss
Vss
13
Todays Unrestricted Routing
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Future Metal Restrictions
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Implications to Design

• Design fabric will be Regular
• Will look like Sea-of-transistors interconnected
  with regular interconnect fabric
• Shift in the design efficiency metric
• From Transistor Density to Balanced Design
• Interconnect RC not a major issue
• Benefits of custom design (performance, density)
  will diminish

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Technology Outlook
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Reliability
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Implications to Reliability

• Extreme variations (Static Dynamic) will result
  in unreliable components
• Impossible to design reliable system as we know
  today
• Transient errors (Soft Errors)
• Gradual errors (Variations)
• Time dependent (Degradation)

Reliable systems with unreliable components
Resilient mArchitectures
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Implications to Test

• One-time-factory testing will be out
• Burn-in to catch chip infant-mortality will not
  be practical
• Test HW will be part of the design
• Dynamically self-test, detect errors,
  reconfigure, adapt

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In a Nut-shell
Yet, deliver high performance in the power cost
envelope
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Summary

• Moores Law is alive and well
• Multi is the key solution
• Many and too many cores, longer term
• Not just for power and performance
• But to deliver highest performance in the power
  envelope with resiliency
• Reliable Systems
• with
• Unreliable Components