NASAGSFC Building 2, Room 24 9 AM EDT, 22 August 2002

1
NASA/GSFC Building 2, Room 249 AM EDT, 22
August 2002

• HET Overview and
• Software Requirements Tycho von
  Rosenvinge
• HET On-Board Processing Tycho von
  Rosenvinge
• Data Formatting / PH Sampling Don Reames
• SIT On-Board Processing Glenn Mason
• Flight Software Design Tom Nolan
• GSE Software Suite Tom Nolan
  Kristin Wortman

2
HET Overview and Software RequirementsTycho
von RosenvingeDonald Reames

• 22 August 2002

3
Personnel

• GSFC
• Bob Baker, Electronics Engineer, CPU24 Design,
  baker_at_lheapop.gsfc.nasa.gov
• Phong Le, Programmer, CPU24 software development
  environment
• Tom Nolan, Programmer, On-board Software,
  tnolan_at_phillips.exeter.edu
• Don Reames, Scientist , GSFC Software Lead,
  reames_at_lheavx.gsfc.nasa.gov
• Larry Ryan, Electronics Engineer, HET
  Electronics, larry_at_milkyway.gsfc.nasa.gov
• Tycho von Rosenvinge, Scientist, HET Design,
  tycho_at_milkyway.gsfc.nasa.gov
• Kristin Wortman, Programmer, On-board GSE
  Software, wortman_at_lheapop.gsfc.nasa.gov
• U of MD
• Glenn Mason, Scientist, Overall SIT Design,
  mason_at_sampex3.umd.edu
• Mihir Desai, Scientist, SIT Data Analysis,
  desai_at_uleis.umd.edu
• Joe Dwyer, Scientist, On-board Software, Florida
  Institute of Technology
• Peter Walpole, SIT Electronics Engineer,
  walpole_at_sampex.umd.edu

4
Relevant Documents

• STEREO HET CPU24 Flight Software Requirements
  Document
• STEREO SIT CPU24 Flight Software Requirements
  Document
• STEREO SEP LET and Central MISC Flight Processors
  Software Requirements Document
• STEREO SEP HET and SIT CPU24 Processors Flight
  Software Development Plan
• CPU24 MISC Documentation (Bob Baker)
• HET PHA Test Software (Tom Nolan)
• Serial Port Interface to TCP/IP (SPiT)
  Programmers Reference (Tom Nolan)
• Caltech PHA ASIC Users Manual (Rick Cook)
• STEREO HET Telemetry Formatting (Don Reames)
• HET to SEP Central Interface Control Document
  (Caltech)
• STEREO MOC to POC and to STEREO Science Center
  ICD (APL)

5
Relevant Documents Contd

• Many of the relevant documents and the PowerPoint
  presentations for this review may be found at
• http//epact2.gsfc.nasa.gov/STEREO/docs.html

6
OVERVIEW

• HET and SIT parts of IMPACT
• Caltech PHA ASIC
• ASIC Test Chip
• CPU24 MISC
• High Energy Telescope (HET)
• GSE
• HET On-Board Processing
• HET Telemetry Formats
• SIT On-Board Processing
• Software Development Environment
• Software Design
• Test ASIC Support Software
• GSE

7
IMPACT Block Diagram
8
Overall SEP Block Diagram
9
Caltech PHA ASIC/Hybrid

• ASIC contains all front-end signal pulse
  processing electronics for silicon detectors in
  HET and LET.
• ASIC has 16 complete dual-gain PHAs, each with
• Preamplifier, configurable to various detector
  capacitances and output ranges
• Two complete shaping amplifier linear gate
  Wilkinson ADC chains, with combined dynamic range
  of 10,000 (full scale/threshold)
• Programmable thresholds
• Bias switching to enable or disable power
• 23-bit scalar for counting trigger rate.
• ASIC is mounted on a ceramic substrate with
  passive support components and installed in an
  80-pin Kovar hybrid package
• ASIC designed by W.R. Cook / Cal Tech (LET
  Electronics Engineer)

10
Caltech PHA ASIC/Hybrid Contd

• Multiple ASICs (if needed) are daisy-chained for
  commanding and data readout
• Sparse readout of PHAs and rate counters
• only PHAs which have been triggered are read out
• high gain PH is read out unless it has the
  maximum value, in which case the low gain PH is
  read out
• token out is used to determine when the last
  pulse height has been read

11
Caltech ASIC Test Chip

• Testing of PHA ASIC for HET
• Test bed supplied by Cal Tech includes ASIC and
  all support components, including CPU24 MISC,
  mounted on a PC board, but without the hybrid
  package
• Software environment for testing is totally
  flight-like (commands, data, interrupts)

12
CPU24 MISC

• Minimal Instruction Set Computer
• 24 bit CPU core
• Dual Stack Architecture
• Data Stack, 17 deep
• Return Stack, 33 deep
• Four 6-bit instructions per word
• Seven interrupts
• 3 UART, event, sec, min, ext
• 8 MHz Instruction Rate

13
HET ACTEL CHIP

• CPU24
• Memory Interface
• 128K words SRAM (Honeywell HLX6228)
• 16 words on chip boot ROM
• Loads program via command UART
• UARTS
• Command, Command Response, Data
• 57600 Baud
• Live Time Counter
• 15-bit prescaler of gated 32 MHz
• 16-bit Gray Code counter, counts units of 1.024
  msec
• Sync Signal Interface
• One second, one minute interrupts

14
HET ACTEL CHIP Contd

• Interface to PHA ASIC
• PHA Readout Sequencer
• Test Pulse Frequency Generator
• Coincidence Logic
• ASIC Commanding

15
CPU24 Design Status

• CPU24 (v2) is based on Cal Tech MISC11 design
• Data UART, live time counter, sync signal
  interface added
• Design coded in Verilog
• Synthesized using Synplify Pro 6.2.4
• PR using Actel Designer 4.0.4.4
• Usage 81 of S cells, 65 of C cells of A54SX72A
• Running on Cal Tech Test Board
• Users Manual Written

16
HET Telescope Schematic
17
HET Performance Requirements
18
HET H1 Detector
19
HET Block Diagram
20
HET Front-End Processing
N
N
Y
N
21
Pulse Height Format from ASIC(LSB-gtMSB)

• struct COMP_PH
• unsigned ph 11
  // bits 0-10
• unsigned overflow 1 //
  bit 11
• unsigned reserved1 1 //
  bit 12
• unsigned reserved2 1 //
  bit 13
• unsigned lohigain 1 //
  bit 14
• unsigned pha_addr 4 //
  bits 15-18
• unsigned chip_addr 4 //
  bits 19-22
• unsigned token 1
  // bit 23

22
Top Level Requirements for HET CPU24 Code (1)

• Boot up CPU24
• Download/decompress tables and CPU24 code from
  SEP Central EEPROM
• Receive Commands from SEP Central
• Receive and handle commands to configure PH ASICS
  (846 bits each)
• Receive and handle commands to patch RAM
• Receive and handle TBD miscellaneous commands
• Echo commands to SEP Central
• Read Hardware Rate Counters
• Read PH Events from ASICs
• Queue PH Events According to Types
• Process PH Events into Software Counters
  (on-board particle identification described
  later)
• Identify High Rate Conditions (switch H1o to low
  gain only switch back depending upon H1i rate
  switch only on 1-minute boundaries)

23
Top Level Requirements for HET CPU24 Code (2)

• Acquire Housekeeping Data and Readout to SEP
  Central
• Generate On-board Pulser Events (set STIM bit)
• Write Out Telemetry Packets Once Per Minute
• Selected PHs (compress 23 bit ASIC pulse height
  to 16 bits)
• Software Counter Rates (24 to 16 bit rate
  compression)
• Hardware Rates (24 to 16 bit rate compression)
• Housekeeping
• Beacon Data
• Include Checksum for Each Packet
• SEP Central expects HET Data Packets Only During
  100 ms Windows Following 1- Second Timer Pulses
  0, 3, 6, , 57 of Each Minute (0 or more packets
  per window preferably spread out over 1 minute
  interval)
• Control Operational Heater?

24
Top Level Requirements for HET CPU24 Code (3)

• Background Tasks
• STIM Pulser Sequence
• Check checksums for on-board code and tables
• Slow readout of on-board code and tables to the
  ground
• Refresh PH ASIC command state once every minute
  ???
• Monitor each preamp output voltage and adjust
  leakage currents as necessary to keep in
  specified range
• HET is assigned 6 data packets (272 bytes each,
  including 12 bytes of CCSDS header) for readout
  once per minute. In addition, Beacon Data,
  Command Echoes, and Housekeeping Data are
  combined into corresponding SEP Central packets.
• HET Beacon Data
• protons 13-30 Mev
• protons 30-50 MeV
• protons 50-100 MeV
• He 13-30 MeV/n

25
Interrupts

• 1-Second Interrupt
• Increment second clock
• 1-Minute Interrupt (double pulse at 1-second
  interrupt)
• Rate counters read out
• PH event buffer formatted into science packets
• End-Of-Frame flag set
• Zero out counters
• Clear event buffers and queues
• Serial Command In Interrupt
• Read next command byte from command UART

26
Interrupts (contd)

• Serial Command Out Interrupt
• Next byte received from command buffer
• Transmit command responses (ASCII)
• Serial Data Out Interrupt
• Send data byte to SEP Central MISC
• Pulse Height Analyzer Interrupt
• pulse-height values for an event are read out
  using a 24-bit wide bus (the G-bus )

27
HET Counting Rates
28
HET Operation During High-Rate Periods

• Requirement Provide composition and energy
  spectra measurements
• over conditions ranging from quiet-time to the
  largest solar events
• Issue During very high-rate periods (e.g., peak
  of Bastille Day 2000 event)
• the single-detector count rates, especially on
  the front detector, will exceed
• 100,000/sec, swamping the system
• Approach (Similar to LET)
• H1 detector has bull's-eye design with smaller
  central area
• Collimation of H1 detector to shield against
  wide-angle protons
• Sides of telescope shielded to reduce H2 to H6
  count rates
• Adjust threshold on H1o to reduce overall count
  rate while maintaining
• energy and species coverage

29
HET Operation During High-Rate Periods Contd

• Threshold adjusted by disabling high-gain
  response of H1o and
• raising threshold of H1o low gain section to
  20 MeV
• Adjustments controlled on-board by H1i
  count-rate (not adjusted)
• Implementation
• H1o threshold raised from 0.2 to 20 MeV when H1i
  singles rate reaches 4000 counts/second. Resume
  low rate configuration when H1i singles rate
  falls below 2000 counts/second.

30
HET GSE Configurations

• GSE to ASIC Test Board (GSFC)
• GSE to HET CPU24 (GSFC)
• GSE (via TCP/IP or data file) to S/C simulator to
  IDPU simulator to SEP Central to HET CPU24
  (Caltech)
• GSE (via TCP/IP or data file) to IMPACT POC A or
  POC B to MOC to S/C to IDPU to SEP Central to HET
  CPU24 (APL and Post-launch)

31
Top Level requirements for HET GSE Code

• Boot ASIC Test MISC
• Boot HET CPU24 in Absence of SEP Central
• Upload on-board tables and HET Code in Absence of
  SEP Central (or to SEP Central)
• Provide User-Friendly Interface for Formatting
  ASIC Commands (846 bits each!)
• Send Commands via ASCII Hex retain memory of
  current ASIC command state
• Send commands to patch HET RAM (also HET
  EEPROM??)
• Display PH Data
• Display STIM Event Data
• Display Rate Data
• Decompress 16 bits to 24 bits

32
HET On-Board Particle Identification

• Tycho von Rosenvinge
• Donald Reames
• 22 August 2002

33
HET Simulations
34
HET Response
35
HET Composite Response (Delta E vs Residual E
Plot)
Fe
Si
O
N
C
4He
3He
protons
electrons
36
HET Composite Log Response
Fe
Si
O
N
C
4He
3He
protons
electrons
37
CPU24 Processing Flow
38
Science Data Acquisition Pulse Height Events

• Triggered by the PH interrupt
• PH events are queued into four different FIFOs
• Particles stopping in H1 (inner and outer)
• Particles stopping in H2-H5
• Particles penetrating all of HET
• PH events created by the on-board pulser (STIM
  events)
• Count number of pulse height events read into
  CPU24

39
HET Event Queuing Algorithm
40
Science Data Processing

• Select PH events from each class type queue
• Determine species and energy
• Increment the corresponding software rate counter
  
• Respond to the EOF reset
• Reset software counters
• Reset hardware counters
• Clear event queues

41
HET On-Board Pulse Height Processing
42
Rate Counter Categories

• Total events processed (STIM events not included)
• Queued H1 events (inner and outer)
• Queued stopping events (H2-H5)
• Queued penetrating events (H1-H6)
• Invalid events
• No H1 (inner or outer)
• Incorrect ordering of pulse heights
• Duplicate H1s
• H1i and H1o
• Inconsistent Particle Type Counter
• consistency check for particles reaching at least
  H3
• particle type should be same for H1 vs
  H2H3H4H5 as for H2 vs H3H4H5
• Singles Rates (counted in ASIC)

43
Science Event Data Processing

• Software count binning according to species and
  energy intervals
• 2 log lookup tables
• Delta E
• Residual E
• Memory required
• log tables 512 24-bit words 2 tables 1024
  words
• Processing and binning of each particle
• SWCtr128128, PrtclType6464 (16,384
  words 4096 words 20 KW)
• Penetrating Particles TBD

44
Stopping Particles Species Energy Intervals
electrons 0.7-1.4, 1.4-2.8, and 2.8-4.0 MeV 78
Stopping particle bins total, including 3
background bins
45
Software Development Approach

• Scientists provide algorithms in C code (HET) or
  FORTRAN (SIT)
• Scientists provide simulated data for testing
  on-board code
• Programmers translate C/FORTRAN to MISC assembly
  language
• Scientists/engineers/programmers test on-board
  software
• Test Plan/Problem Reporting and Tracking
• See sections 3.7.2 and 3.7.4 of FSWDP
• Configuration Management (See section 3.7.3 of
  FSWDP)

46
Mapping PH Channels to Log Space

• PH gain(channels/MeV) Energy Loss (MeV)
  Offset
• PHmin gain Emin Offset, PHmax gain Emax
  Offset
• Want to map interval Emin (MeV) - Emax(MeV) to
  Log2 interval
• 0 128 i.e.
• logch a log2(PH-Offset) b
• 0 a log2(Emin) b and
• 128 a log2(Emax) b
• 0 a log2( (PHmin-Offset) / gain) b
• 128 a log2( (PHmax-Offset) / gain) b
• or
• logch (4 a log2(PH-Offset) 4 b) gtgt 2,
  where
• a 128 / log2( (PHmax Offset) / (PHmin
  Offset) )
• b - 128 log2(PHmin Offset) /
  log2((PHmax-Offset)/(PHmin-Offset))

47
HET On-Board Code Snippets - I
// Code to Create On-board Table for Obtaining
DeltaE Log Channelonly the table and bDeltaE are
on-board define TBLSZ 512 double log2(double
x) return log(x)/log(2.) int roundoff(double
x) if(xgt0.0) return (int)(x0.5)
else return (int)(x-0.5) // Initialize
Look-up Table CDeltaEroundoff(4.Nlogchs/log2(De
ltaEmax/DeltaEmin)) bDeltaEroundoff(-4.Nlogchs
log2(DeltaEphmin)/log2(DeltaEmax/DeltaEmin)) Tabl
eCDeltaElog200 for(i1iltTBLSZi)
TableCDeltaElog2iroundoff((double)CDeltaElog2(
(double)i))
48
HET On-Board Code Snippets - II
// On-Board int CDeltaElog2(int ph) //
note ph is the ph one would have obtained if the
entire dynamic range
// were covered by a single
PHA with gain equal to the high gain int
n0 while(phgtTBLSZ-1) // need to hardcode
TBLSZ-1 on-board to avoid repeated subtraction of
1 phgtgt1 nCDeltaE retur
n (TableCDeltaElog2phn) // log compressed
DeltaE channel by table lookup
(CDeltaElog2(DeltaEph)bDeltaE)gtgt2