Subwavelength Design: Lithography Effects and Challenges Part II: EDA Implications

1
Subwavelength Design Lithography Effects and
Challenges Part II EDA Implications

• Andrew B. Kahng, UCLA Computer Science Dept.
• ISQED-2000 Tutorial
• March 20, 2000

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Forcing Trends in EDA

• Silicon complexity and design complexity
• many opportunities to leave major on the
  table
• issues physical effects of process,
  migratability
• design rules more conservative, design waivers
• device-level layout opts in cell-based
  methodologies
• Verification cost increases dramatically
• Prevention a necessary complement to checking
• Successive approximation design convergence
• upstream activities pass intentions, assumptions
  downstream
• downstream activities must be predictable
• models of analysis/verification objectives for
  synthesis

3
EDA Awareness of Process

• EDA wants to know as little as possible
• This part of tutorial the unavoidable issues

4
Necessary Formulations, Flows

• Upstream objectives want to capture downstream
  layout operations transparently
• New problem formulations
• PSM more global phenomena, scalability issues
• OPC mostly local phenomena
• function-driven corrections
• hierarchical and reuse-centric regimes
• New tool integrations

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Phase Smart Custom Layout
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Phase Smart Place and Route
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Phase Smart Verification
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• Global phenomena in PSM phase layout

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Phase Assignment in PSM

• Assign 0, 180 phase regions such that
• (dark field) feature pairs with separation lt B
  have opposite phases
• (bright field) features with width lt B are
  induced by adjacent phase regions with opposite
  phases

(Dark field, neg resist)
? b
b ? minimum separation or width, with phase
shifting B ? minimum separation or width,
without phase shifting
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Conflict Graph

• Vertices features (or phase regions)
• Edges conflicts (necessary phase
  contrasts)
• (feature pairs with separation lt B )

lt B
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Odd Cycles in Conflict Graph

• Self-consistent phase assignment is not possible
  if there is an odd cycle in the conflict graph
• Phase-assignable ? bipartite ? no odd cycles

0 phase
180 phase
??? phase
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Breaking Odd Cycles

• Must change the layout
• change feature dimensions, and/or
• change spacings
• PSM phase-assignability is a layout, not
  verification, issue

? B
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Bright-Field (Positive-Resist) Context

• Every critical-width feature defined by
  opposite-phase regions
• Regions not defined a priori

black boundaries b/w 0 and 180 areas (to be
deleted)
green 180-shift
red odd degree
blue features
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Value Proposition to Designers

• 0.10mm feature sizes in production in 1999
• ?2x performance
• Higher yield
• Transparent to designer

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Problem Statements I

• Develop efficient algorithms for minimum-cost
  phase region definition and phase assignment in
  bright-field context
• open definition of cost (mfg difficulty, area,
  )
• Continuum between sparse, dense criticality
• DF Alt PSM BF binary trim mask approach simple
  and elegant for sparse critical features
• what about when all features are critical?
• (full-chip area opt, in addition to gate
  shrink)
• can be treated as a routing problem (of phase
  edges)

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Problem Statements II

• New logic (mapping) and performance optimization
  formulations
• with phase shifting, gate lengths and wire widths
  continuously variable between b and B
• without phase shifting, gate lengths and wire
  widths must be at least B
• not all features can be phase-shifted
  function-driven
• What is optimal choice of phase-shifted
  features, and their sizes?

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Problem Statements III

• Understand PSM implications for custom layout
• define a taxonomy of phase conflict
• no set of traditional design rules can handle all
  phase conflicts what are good layout
  practices?
• no Ts on poly
• fingered transistors should have even-length
  fingers
• etc.
• Address PSM as a multi-layer problem
• e.g., conflict can be solved by re-routing a
  connection to another layer

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Layer Assignment
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• Local phenomena in OPC

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Problem Statements IV

• Pass functional intent down to OPC insertion
• OPC insertion is for predictable circuit
  performance, function
• Problem make only corrections that win ,
  reduce perf variation (i.e., link to performance
  analysis, optimization) ?
• Pass limits of mask verification up to layout
• Problem avoid making corrections that cant be
  manufactured or verified

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Problem Statements V

• Minimize data volume
• Problem make corrections that win , reduce
  perf variation up to some limit of data volume
  for resulting layout ( mask complexity, cost)
• Layout needs models of OPC insertion process
• Problem taxonomize implications of layout
  geometry on cost of the OPC that is required to
  yield function or faithfully print the geometry
• find a realistic cost model for breaking
  hierarchy (including verification,
  characterization costs)

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• Hierarchical and Reuse-Centric Contexts

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Issues Raised by Hierarchy, Reuse

• Large data volume and verification costs when
  hierarchy is broken -- but PSM and OPC are both
  context-dependent!
• Standard-cell approach requires absolute
  composability of cells -- this must somehow be
  guaranteed as we move into PSM regime

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Problem Statements VI

• Given a cell library, what is its flexibility
  (i.e., composability with respect to PSM) ?
• Given a standard-cell layout and allowed increase
  in hierarchical layout data volume, what is the
  maximum reduction in area obtainable by creating
  new cell masters with different phase layout
  solutions?
• Given a standard-cell layout with phase-solution
  instantiations that induce conflicts, what is
  minimum-cost removal of phase conflicts?
• DOFs change instance, shift, space, mirror, ...

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Integrated Layout Flow, 1

• Gate-level netlist, performance constraint
  budgeting, early context (mask/litho technology,
  area density...)
• Standard-cell placement with integrated
  compatibility awareness (composable PSM layouts)
• Global and detailed routing, cell resynthesis on
  fly
• delay, noise, reliability assumptions
  constraints
• OPC- and PSM-aware min-cost layout synthesis
  subject to constraints (e.g., minimize costs of
  breaking hierarchy, follow good practices,
  etc.)
• fill abstractions (for parasitic extraction) in
  constraint-driven routing

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Integrated Layout Flow, 2

• Density analysis, CMP-fill estimation based on
  detailed routing
• Post-detailed routing performance analysis
• PSM phase assignability check for all layers
• new compaction constraints as necessary
• layout compaction or incremental detailed routing
• until pass phase assignability, performance
  analysis
• note integration with full-chip geometric
  compaction!
• Actual dummy fill insertion
• issues data volume

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Integrated Layout Flow, 3

• Detailed physical verification (geom, conn, perf)
• Full-chip OPC insertion
• issues min-cost OPC that achieves required
  function
• issues data volumes, metrics, intermediate
  formats
• issues tools stepping on each other (line
  extensions in DSM router rules are zeroth-order
  OPC, for example)
• Full-chip printability check
• Silicon-level DRC/LVS/performance analysis

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Conclusions

• New problem formulations
• PSM layout practices, automated full-chip and
  standard-cell compatible solutions
• OPC taxonomy of local phenomena, data reduction
• function-driven corrections (can filter
  complexity)
• hierarchy, data volume, reuse concerns
• New tool integrations
• compaction, on-the-fly cell synthesis,
  incremental detailed routing
• graph-based (verification-type) layout analyses
• new performance opts, even logic opts

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• Example Details I
• Automatic Conflict Resolution

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Compaction-Oriented Approach

• Analyze input layout
• Determine constraints for output layout
• new PSM-induced (shape, spacing) constraints
• Compact (e.g., solve LP) with min perturbation
  objective
• e.g., minimize sum of differences between old and
  new positions of each edge
• Key Minimize the set of new constraints,
  i.e., break all odd cycles in conflict graph by
  deleting a minimum number of edges.

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One-Shot Phase Assignment
conflict graph
find min-cost edge set to be deleted for
2-colorability
phase assignment
compaction
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Conflict Graph

• Dark Field build graph over feature regions
• edge between two features whose separation is lt B
• Bright Field build graph over shifter regions
• two edge types
• adjacency edge between overlapping phase regions
  endpoints must have same phase
• essentially, these regions must be merged into
  single phase shifter
• DRC-like (gap, notch type) local rules must
  likely be applied to such merging
• conflict edge between shifters on opposite side
  of critical feature endpoints must have
  opposite phase
• Step 3 simple reduction to previous
  (dark-field) T-join solution each dotted edge
  becomes a 2-chain (introduce one extra vertex)

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Conflict Graph

• Dark Field

green feature red conflict
conflict graph G

• Bright Field

conflict edge
conflict graph G
adjacency edge
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Conflict Graph for Cell-Based Layouts

• Coarse view at level of connected components of
  conflict graphs within each cell master
• each of these components is independently
  phase-assignable
• can be treated as a single vertex in
  coarse-grain conflict graph

cell master A
cell master B
connected component
edge in coarse-grain conflict graph
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Detail Conflict Edge Weight

• Conflict edges not on critical path break for
  free
• Or, use min-perturbation objective

critical path
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F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
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Black points - shifters Blue - shifter
overlap Thick edges - critical
Bipartization Problem delete min of thin
edges to
make graph bipartite
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Black points - features Blue - shifter
overlap Pink - extra nodes to distinguish
opposite shifters
Bipartization Problem delete min of nodes (or
edges)
to make graph bipartite
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Black points - shifters Blue - shifter
overlap Thick edges - critical
Bipartization Problem delete min of thin
edges to
make graph bipartite
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Black points - features Blue - shifter
overlap Pink - extra nodes to distinguish
opposite shifters
Bipartization Problem delete min of nodes (or
edges)
to make graph bipartite
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Key Technique Reduction to T-join

• Goal delete minimum-cost set of edges from
  conflict graph G, so as to eliminate odd cycles
• Construct geometric dual graph D dual(G)
• Find odd-degree vertices T in D
• Solve the T-join problem in D
• find min-weight edge set J in D such that
• all T-vertices have odd degree w.r.t. J
• all other vertices have even degree w.r.t. J
• Solution J corresponds to the desired min-cost
  edge set in conflict graph G

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Optimal Odd Cycle Elimination
dark green feature red conflict
conflict graph G
T-join of odd-degree nodes in D
dual graph D
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Optimal Odd Cycle Elimination
dark green feature red conflict
- assign phases dark green and purple -
remaining red conflicts correctly handled
corresponds to broken edges in original conflict
graph
T-join of odd-degree nodes in D
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T-join Problem in Sparse Graphs

• Reduction to matching
• construct a complete graph T(G)
• vertices T-vertices
• edge costs shortest-path cost
• find minimum-cost perfect matching
• Typical example sparse (not always planar)
  graph
• note that conflict graphs are sparse
• vertices 1,000,000
• edges ? 5 ? vertices
• T-vertices ? 10 of vertices 100,000
• Drawback finding all shortest paths too slow and
  memory-consuming
• vertices 100,000 edges 5,000,000,000

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T-join Problem Reduction to Matching

• Desirable properties of reduction to matching
• exact (i.e., optimal)
• not much memory (say 2-3Xmore)
• results in a very fast solution
• Solution gadgets!
• replace each edge/vertex with gadgets s.t.
• matching all vertices in gadgeted graph
• Û T-join in original graph

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T-join Problem Reduction to Matching

• replace each vertex with a chain of triangles
• one more edge for T-vertices
• in graph D m edges, n vertices, t T
• in gadgeted graph 4m-2n-t vertices, 7m-5n-t
  edges
• cost of red edges original dual edge costs
  cost of (black)
  edges in triangles 0

vertex in T
vertex ? T
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Example of Gadgeted Graph
Gadgeted graph
Dual Graph
black red edges min-cost perfect matching
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Results

• Runtimes in CPU seconds on Sun Ultra-10
• Greedy breadth-first-search bicoloring
  (similar to Ooi et al.)
• GW Goemans/Williamson95 heuristic
• Cook/Rohe98 for perfect matching
• Latest improved gadgets runtimes decrease by
  factor of 6

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• Example Details II
• Auto-PR Flow Issues

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Constraints

• PSM must be transparent to ASIC auto-PR
• free composability is the cornerstone of the
  cell-based methodology!
• focus on poly layer we are concerned with
  placer, not router
• Competitive context for placer
• extremely competitive runtime regimes (e.g., 106
  cells detail-placed in 20 min) faster runtimes
  needed in RTL-planning methodologies (Nano/PKS,
  Tera)
• any nontrivial cost of checking placement
  phase-assignability is unacceptable
• Iteration between placer and a separate tool is
  unacceptable
• interface to auto-PR tools is bulky (e.g., 100s
  of MB for DEF), slow
• no known convergent method for post-PR
  phase-assignability checks to drive PR to
  guaranteed correct solution (very difficult!)
• PR tool MUST deliver guaranteed phase-assignable
  poly layer

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Guidelines

• Placer
• no re-entry into placer from an external tool
• any needed extra functionality must be built
  directly into placer
• placer must guarantee a phase-assignable poly
  when finished
• polygon layout information currently not in
  placement vocabulary
• available relevant abstractions pin EEQs/LEQs,
  overlap layer geometries
• side files or LEF extensions needed for, e.g.,
  capturing versioning or phase shifters near
  left/right cell boundaries
• Cell layout
• cell layouts and phase shifters are assumed fixed
  during library creation
• on-the-fly cell layout synthesis or layout
  perturbations generally not allowed
• 2k possible versions (i.e., distinct phase
  bindings) are available for a given master cell
  with k connected components in its phase conflict
  graph, k lt k of which contain critical poly at
  cell boundary
• impractical to use EEQs to capture versioning
  within iterative improvement

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Types of Composability

• Same-row composability
• any cell can be placed immediately adjacent (in
  the same row) to any other cell
• Adj-row composability
• any cell can be placed in an adjacent cell row to
  any other cell, with the two cells having
  intersecting x-spans
• Four cases of cell libraries (G guaranteed NG
  not guaranteed)
• Case 1 adj-G, same-G
• most-constrained cell layout most transparent to
  placer
• Case 2 adj-G, same-NG
• Case 3 adj-NG, same-G
• Case 4 adj-NG, same-NG
• least-constrained cell layout least transparent
  to placer

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Case 2 Adj-G, Same-NG
Blue vertices, edges graph of phase
assignment dependencies
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Case 3 Adj-NG, Same-G
Blue vertices, edges graph of phase
assignment dependencies
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Case 4 Adj-NG, Same-NG
Blue vertices, edges graph of phase
assignment dependencies
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Overlap Layer Abstraction in LEF

• Like teeth of a broken comb defined for each
  master cell
• Placer makes sure that the teeth dont collide
  when the cells are placed, i.e., the two broken
  combs interlace
• Available today in LEF standard placer
  understands overlap layer
• current heuristics may not scale well if many
  instances have overlap geometry

Traditional picture of overlap geometries
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Case 1 Adj-G, Same-G

• Solution 1 no restrictions on the cell layout
• create cell abstractions such that placer runs
  in normal mode
• e.g., pre-bloat (by 1 site) cells that have
  critical poly near left/right boundary
• e.g., create overlap layer obstacles
  corresponding to critical poly near top/bottom
  boundary
• Solution 2 smart rules to restrict cell layout
• e.g., every pair of boundary-CP features from the
  same cell must be non-interfering
• definition two features are non-interfering if
  they are in different connected components of the
  cells phase conflict graph
• no boundary-CP feature is near two different
  sides of its cell
• these two restrictions composability guaranteed
  (no odd cycles possible)
• Solution 3 dumb rules to restrict cell layout
• all cells have 250nm-wide 0-phase boundary
  (IBM-style AltPSM)

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Notation

• M number of master cells in library
• Ci ith master cell, i 1, , M
• wi width of ith master cell, i 1, ,
  M
• Vi number of versions of the ith master
  cell, i 1, , M
• Cik kth version of ith master cell, i
  1, , M k 1, , Vi
• N number of movable cells in the row
  of interest
• Rh hth cell in the row of interest
• Sh master cell corresponding to hth
  cell in row of interest
• boundary-CP critical poly feature near the
  cell boundary

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Cases 2,4 Same-NG

• Each (sub)row checked separately, post-placement
• Basic tool cell compatibility table
• library is precharacterized by M2 two-dimensional
  arrays Aij, one array for each possible pairing
  of cells with Ci to the left of Cj
• Aijltp,qgt minimum site separation at which Cip
  can be placed adjacent to Cjq (p 1, , Vi
  and q 1, , Vj)
• example M 500 with 16 versions of each master
  cell lt 30 MB storage
• Goals
• (1) if phase assignment possible, return set of
  versions for each of the cell instances
• (2) if not possible, return set of versions plus
  set of inserted feedthroughs (extra sites) such
  that minimum perturbation is achieved

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Cases 2,4 Same-NG Example Soln

• Shortest-path finding in a simple graph
  (actually, a DAG)
• for each version j of each cell Ri, create node
  ltRi,jgt, i 1, , N and j
  1, , Vri
• create source node ltR0,0gt and termination node
  ltRN1,0gt
• create directed edges (ltRi,jgt,ltRi1,kgt) for all
  versions j of cell Ri and versions k of cell Ri1
  (weight cost of perturbing placement to
  achieve minimum allowed site separation)
• create zero-weight directed edges (ltR0,0gt,ltR1,jgt)
  for all versions j of cell R1 and (ltRN,jgt,
  ltRN1,0gt) for all versions j of cell RN
• Minimum-perturbation solution (specifies
  compatible versions as well as required changes
  in cell positions) given by shortest path from
  ltR0,0gt to ltRN1,0gt

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Cases 3,4 Adj-NG Example Solns

• Basic cause of problem horizontal poly near
  shared rails
• complex cells that push the cell height
  (pitches), e.g., latch/FF, adder, mux
• Solution 1 partial amelioration by layout
  constraints
• e.g., for horizontal critical poly near power
  rail, the outside shifter must be 0-phase (NTI
  style)
• can be done silently by version compatibility,
  etc.
• Solution 2 abstract w/existing LEF overlap
  layer construct

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Conclusions (again)

• New problem formulations
• PSM layout practices, automated full-chip and
  standard-cell compatible solutions
• OPC taxonomy of local phenomena, data reduction
• function-driven corrections (can filter
  complexity)
• hierarchy, data volume, reuse concerns
• New tool integrations
• compaction, on-the-fly cell synthesis,
  incremental detailed routing
• graph-based (verification-type) layout analyses
• new performance opts, even logic opts
• Non-trivial flow, methodology effects span
  library creation to auto-PR, performance
  optimization, etc.