Fabrication of GaAs on Si heterostructures by hydrogen implantation and

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Fabrication of GaAs on Si hetero-structures by
hydrogen implantation and direct wafer
bonding 06. 09. H.J. Woo, H.W. Choi, G.D.
Kim, W. Hong, J.K. Kim, H.R. Lee Ion Beam
Application Group, KIGAM, Korea
IBA GROUP
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Introduction

• GaAs on Si technology presents a huge potential
  of interest as it combines the superior
  electrical and optical properties of GaAs with
  the mechanical and economical advantages and
  density of integration of silicon.
• To obtain this structure, hetero-epitaxial growth
  has been investigated extensively, but due to the
  large lattice mismatch (4), an unacceptable
  high density (typically gt 107/cm2) of threading
  dislocations could not be avoided.
• Ion-cut concept based on ion implantation and
  direct wafer bonding is recognized as a major
  breakthrough to obtain this structure from
  technical and economical points of view.
• The aim of this paper is to investigate the role
  of implant temperature and ion fluence on
  blistering of the surface after a subsequent
  annealing in detail, and to develop ion-cut
  process allowing GaAs thin film to be transferred
  onto a full silicon wafer.

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Ion-cut process flows for GOI wafers fabrication
Si cleaning
SiO2 deposition on GaAs 300-400 nm PECVD CMP
SOG (300-500 nm) Deposition baking (180?)
Si cleaning

• Proton implantation
• fluence 1.01.6x1017 H/cm2
• implant temp. 120160?

• He-H co-implantation
• He, low dose, RT
• H, high dose, RT

GaAs cleaning
RT bonding
Low-temp. ion-cut splitting (200-230?, 10-15 h)
high-temp. annealing CMP polishing
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Ion-cut technology
Ion implantation technology (precise definition
of layer thickness)

Wafer bonding technology (keeping the original
GaAs quality)

Ion-cut GOI wafers
Schematic of the ion-cut process
for GaAs-on-insulator wafers fabrication
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Hydrogen ion implantation

• GaAs wafer semi-insulating (100) oriented, 2"
  GaAs
• Fluence range 4.0x1016 2.0x1017 H/cm2
• Implant temperature (on wafer surface) 40300?
• Ion flux 1.0x1013 H cm-2s-1

Low Energy Implantation System
Inner view of the target chamber
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Estimated depth profile of hydrogen concentration
for a fluence of 8x1016 H/cm2 at 40 keV in GaAs
wafer
Hydrogen concentration profiles in GaAs implanted
with 8x1016 H/cm2 at different temperatures as
determined by the SIMS analysis.
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Optical microscopic images after proton
implantation (40 keV, 1.6x1017 H/cm2) and/or
annealing. a) as-implanted at 140?, and implanted
at 120? and annealed for 30 min. b) at 300? and
(c) at 400?.
FE-SEM micrographs of GaAs surface with 40 keV
1.6x1017 H/cm2 implant at 120?, following the
annealing step at a) 300? for 30 min and b) 400?
for 60 min.
2 µm
2 µm
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Optimum condition for ion-cut
Approximate temperature windows for microcrack
development by hydrogen ion implantation
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Fluence and temp. boundaries of blister formation
in hydrogen- implanted GaAs

• New optimum temperature window 120160?
• Optimum fluence range 1.0x1017 1.6x1017 H/cm2

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Lattice damage profiling
Random and aligned RBS/channeling spectra for
GaAs single crystals implanted at different
temperatures
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Examination of microstructure
a)
b)
Cross section TEM images GaAs wafer a) after
hydrogen implantation (40 keV, 1.2x1017 cm-2) at
140? and b) after annealing at 300?
Platelet (microcrack, microcavity)
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Rq 12 nm
396 nm 273 nm
GaAs SiO2/SiNx Silicon
FE-SEM image of a transferred GaAs layer onto
silicon wafer via a PECVD oxide layer.
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Summary

• The GaAs ion-cut process is sensitive to both the
  implant temperature and the fluence. At low
  implant temperature (lt100?), hydrogen is unable
  to form into the defect structure responsible for
  blistering, and if the temperature is too high,
  the platelets are not able to evolve and
  blistering is less prolific because of the
  out-diffusion of hydrogen.
• It was found that the optimum implant temperature
  window lie in 120160?, which is relatively lower
  than the previously reported implant temperature
  window probably due to the inaccuracy in
  temperature measurement in other laboratories.
• Thin GaAs layer was successfully transferred onto
  a 100 mmF silicon wafer at 250?, and low
  temperature splitting is of importance for layer
  transfer between dissimilar materials with very
  different thermal expansion coefficients as well
  as for processed wafers containing
  temperature-sensitive devices.