A Codesign and Cosimulation Environment Based on MATLAB/Simulink Models Application to the design of a Common Rail test bench

1
A Codesign and Cosimulation Environment Based on
MATLAB/Simulink ModelsApplication to the design
of a Common Rail test bench

• L.M. Reyneri, E. Bellei, E. Bussolino, L. Mari,
  F. Renga
• September 2002
• Politecnico di Torino

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Part I

• A Typical Design Framework

3
Common Rail Test bench
4
System Specifications
Power Electronics
HW
SW
Mechanical
Electrical
Plant
User Interface
User
Environment
5
Common Rail Test bench
6
Design Partition
Electronics Designer
Control SW Designer
Power Electronics
HW
SW
Mechanical
Electrical
Plant
User Interface
User
Environment
Psychology Law Market
User I/F Designer
Electromechanical Designer
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Partition ? Simulations (?)
SPICE VHDL SystemC VCC
Assembler C/C
Power Electronics
HW
SW
Mechanical
Electrical
Plant
User Interface
Autocad FEM
User
Environment
Visual BASIC
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Intermediate Result
if then else goto linux, ???
Power Electronics
HW
V, A, W, Hz, a, g, ???
SW
Mechanical
Electrical
Plant
User Interface
Windows, mm, icon, click, ???
UNI, inches, degrees, ???
User
Environment
impact user-friendly colours, ???
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Someone will take decisions
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and someone will payfor the mistakes
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Final Result (perfect agreement)
Its YOUR fault !!! my part is fine
Power Electronics
HW
Its YOUR fault !!! my part is fine
SW
Mechanical
Electrical
Plant
User Interface
Its YOUR fault !!! my part is fine
Its YOUR fault !!! my part is fine
User
Environment
Its YOUR fault !!! my part is fine
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Conclusion (but it works)
Power Electronics
HW
SW
Mechanical
Electrical
Plant
User Interface
User
Environment
Patches
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Part II

• HW vs. SW vs. Analog
• Integrated Design

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HW/SW Design Styles and Languages
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Techniques and Platforms
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When do we need HW?

• Complex or high speed functions (counters,
  timers, PWM)
• To reduce complexity of SW (slower sample time,
  smaller CPU)
• Repetitive and/or regular operations
• Reliability

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Traditional HW/SW design
High level languages
System description/specs.
Requires experience
HW/SW partitioning
Critical
HW/SW interfaces
Detailed design
HW
SW
Very expensive loop
Simulation/verification
Does it work?
Very seldom
Enough performance
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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Integrated HW/SW codesign
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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Part III
CodeSimulink environment for HW/SW/mixed-mode
codesign and cosimulation
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Existing Codesign tools
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Codesign under CodeSimulink
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
22
System Description
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Assigning Functional Parameters
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Simulations

• Functional verification
• Parameter tuning, ecc.

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Codesign under CodeSimulink
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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Implementations

• Digital HW different architectures
• Synchronous parallel (base architecture)
• bit-serial (smaller, slower)
• systolic (faster)
• interfaces among architecture
• Analog HW different architectures (under
  developm.)
• Voltage/current single-ended/differential
• Frequency/pulseWidth modulation
• SW different CPUs
• External/Simulink to simulate external world
  (plant, actuators, sensors, environment, etc.)

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HW/SW partitioning (manual)
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Implementation parameters

• DATAWIDTH (number of bits)
• BINARYPOINT (position of fixed point)
• REPRESENTATION ((un)signed, sign/modulus)
• OVERFLOW (saturation/wraparound)
• TRUNCATION (floor, ceil, round, etc.)
• PIPELINE (latency, speed)

3.50
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Different Data Types

• Scalars (one data per sample)
• Vectors (a vector of data per sample mux/demux)
• serial (data sequentially on a single channel)
• parallel (data in parallel on different channels)
• Matrices (a matrix of data per sample for
  instance images in TV or vision)
• serial
• parallel/serial
• serial/parallel

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Serial and parallel vectors
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Assigning HW parameters
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Parameters are associated with signals
Parameters assigned with output ports !
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Adding interfaces between architectures

• Block to block automatic (e.g. HW synchronous
  data-flow protocol)
• HW/SW they depend on chosen platform (see
  further)
• digital/analogue they depend on A/D, D/A
  converters
• HW/external, SW/external (encoder, PWM, A/D.D/A,
  etc.) they have appropriate parameters

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Synchronous data-flow protocol

• If source has a valid data (VAL), and
• if destinations are ready to receive it (RDY),
• then data is transferred at next clock edge
• Guarantees correct timing!

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Post-assigning simulations(bit-accurate)
6,-6
6,0
6,-2
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Codesign under CodeSimulink
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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Quick Performance Estimation

• Every cell has an (approximate) performance model
  which depends on
• technology (HW/SW/analogic)
• architecture (parallel, bit-serial, etc.)
• accuracy --gt num. bit (HW), power (anal.),
  etc.
• CodeSimulink accumulates performance
• Quick performance estimation, without
  time-consuming compilation

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Quick performance estimation
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Quick performance estimation
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Performances

• Number of cells (FPGA) or area (ASIC)
• Power dissipation (battery duration...)
• Latency (computing delay)
• Max. clock Frequency (not yet)
• Max sample frequency
• Code and data size (RAM size)
• Accuracy (S/N, bit number), from simulations

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Codesign under CodeSimulink
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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CodeSimulink compilation

• Separation of multiple platforms
• Hierarchy removal (flattening)
• Separation of SW, digital HW, analog HW blocks
• Adding interfaces
• Translation CodeSimulink (SW) --gt C (RTW)
• Translation CodeSimulink (digital) --gt VHDL
• Translation CodeSimulink (analogic) --gt EDIF

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HW/SW Compilation

• Possibility to edit VHDL/C/EDIF code
• Compilation VHDL --gt ASIC, FPGA (Altera, Xilinx,
  others) (Leonardo - Mentor Graphics proprietary
  tool)
• Compilation C --gt executable (ANSI C compiler)
• Post-compilation performance evaluation

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Every cell is made of...

• Simulink symbol
• Fast functional model for simulations (template)
• Performance estimation model (SW, HW, )
  (template)
• VHDL, EDIF, C description (template)
• Parameter editing mask (template)
• Documentation (template)

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Codesign under CodeSimulink
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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Platforms

• SW-only (CPU, microprocessors, PCs, etc.)
• HW-only (ALTERA, XILINX, ASIC, etc.)
• HW/SW
• board (CPUFPGA)
• Systems-on-chip (ASIC coregates)
• Programmable systems-on-chip

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A few commercial platforms

• SIDSA HDST100 board (ARM7TDMI Altera 10k100)
• SIDSA HDST200 board (ARM7TDMI Altera 10k100)
• SIDSA FIPSOC chip (80C51 FPGA)
• SUNDANCE HDT355 board (TMS320C30 Altera
  10k100)
• SUNDANCE HDT367 board (ARM Xilinx Virtex)
• TRISCEND chip (80C51 FPGA)
• TRISCEND chip (ARM7TDMI FPGA)
• ALTERA Excalibur chip (ARM7TDMI FPGA)

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CodeSimulink Libraries

• Basic Simulink (, , integr. deriv. mux,
  demux, in, out, filters, f(x), 1/z, sources,
  scopes, etc., etc., etc.)
• Toolboxes (image processing, neuro-fuzzy,
  flowchart)
• Application-dependent (under request)

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Codesign under CodeSimulink
System description/specs.
High level languages
Functional simulation
High level simulator
HW/SW partitioning
Automatic/driven/manual
Fast performance estimation
Very quick loop
Enough performance?
Compilation
HW
SW
Automatic
ASIC/FPGA
DSP/PC
Programmation
(System-on-chip)
Assembly and testing
Often yes, but
Enough performance?
Production
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Advantages (Code)Simulink
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Applications

• Control, image processing, neuro-fuzzy networks
• Design of consumer electronic circuits
• Design of high performance circuits
• Not suited to design microprocessors
• Speeding-up Simulink simulations, running on HW
  (limited resolution)

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Project Status (obsolete)

• Compiler is complete
• Synchronous parallel library is complete
• Other libraries are under development
• New technologies/platforms to be characterized
  (semi-automatic procedure)
• We are looking forward to cooperate (e.g. joint
  development of applications)

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Other Simulink-based tools

• There are other commercial HW design tools based
  on Simulink
• DSP Builder from Altera
• System Generator from Xilinx
• These are mostly HW-only design tools (using
  Simulink as an HDL language)

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Advantages of CodeSimulink

• Handles both digital and SW and analog and RF and
  mixed-signal SoCs
• Automatically takes care of data exchange and
  timing (HW/HW, HW/SW, digital/analog)
• Accurate high-level functional models of digital,
  analog, RF and mixed-signal interactions
• High-level performance modeling (power, speed,
  area, code size, etc.)
• Supports FPGA and ASIC and programmable SoC

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Advantages of CodeSimulink

• Natively handles scalars, vectors, matrices
• Supports multi-platforms, multi-cores (multi-SW,
  multi-HW, hybrid)
• Supports Visual Basic / Windows GUIs
  (simulations and compilation)
• Supports bit-parallel, bit-serial, systolic data
  paths and bundled-data asynchronous design (under
  developm.)
• Interfaces to low-level simulators (ModelSim,
  MaxPlus, Quartus, Xilinx, Spice-like)

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Limitations of (Code)Simulink

• Data-dominated systems
• Mostly fixed time sampling strategy (multirate)
• Library-based (sub-optimal)
• Models require technology characterization

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Commercialization of CodeSimulink

• Free for universities for academic purposes
• Sundance ltd. is going to commercialize this
  product at end of May 2003

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Part IV

• Application of CodeSimulink to the design of a
  Common Rail Test bench

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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Common Rail Test bench
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Part V

• CodeSimulink HW/SW Codesign tool
• Internal operation

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Index

• HW/SW Compilation (L. Mari)
• Quick Performance Estimation (A. Serra)
• HW Performance Models (A. Cerrato)
• SW Performance Models (M. Lazarescu)
• Numeric optimization (G. Belforte)
• HW/SW Platforms (M. Chiaberge)