Programmable ASICs

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Chapter 4

• Programmable ASICs

Application-Specific Integrated CircuitsMichael
John Sebastian Smith Addison Wesley, 1997
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Programmable ASICs

• Two basic types of programmable ASICs
• Programmable Logic Device (PLD) - first developed
  as small programmable devices that can replace a
  handful of TTL parts
• least complex ones are a simple AND/OR PLA with
  latches on the outputs and feedback paths to the
  inputs of the array
• Field Programmable Gate Array (FPGA) - more
  complex devices that can hold up to 100K gate
  equivalents or more
• some implemented as symmetrical arrays of simple
  logic devices
• others include more complex and specialized logic
  blocks
• An FPGA (or PLD) is an IC that is fabricated with
  some connections missing
• The user (designer) creates a design to be placed
  on the FPGA using design entry and simulation
• Automatic tools create a string of bits (a
  configuration file) describing the extra
  connections necessary to program the FPGA to
  perform the required function
• A device programmer is then (usually) used to
  load the configuration file into the FPGA

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FPGA Components

• FPGAs have several basic components
• Regular array of basic (programmable) logic cells
• Level of complexity and number of different types
  of logic cells differs across manufactures and
  even across families from the same manufacturer
• Programmable interconnect for connecting the
  basic cells into different configurations
• Programming technology for configuring the cells
  and programmable interconnect
• One-time-programmable (OTP)
• Erasable
• Programmed on power-up
• Custom software used by the designer to create
  the configuration file

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Programming Technology - the Antifuse

• An antifuse is normally open
• A high programming voltage is placed across it
• This forces a programming current (about 5 mA)
  through it which melts the thin insulating
  dielectric forming a permanent, resistive silicon
  link

Figure 4.1 An Actel antifuse. (a) A cross
section. (b) A simplified drawing. (c) From
above, an antifuse is approximately the same size
as a contact.
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Actel Antifuses

• Actel antifuse technology uses three additional
  masks over a traditional CMOS process
• Programming an ACTEL device requires about 5 to
  10 minutes per device
• Production programming of more than 1000 or 2000
  devices per week requires a gang (multiple
  device) programmer

Table 4.1 Number of antifuses on Actel FPGAs
Figure 4.2 Distribution of resistances for blown
Actel antifuses.
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Quicklogic Metal-Metal Antifuse

• Metal-metal antifuses directly connect metal
  wiring layers - thus eliminating the parasitics
  of a polysilicon layer in between
• Direct connections to the metal layers make it
  easier to use larger programming currents
  producing a lower antifuse resistance

Figure 4.3 Metal-metal antifuse. (a) An idealized
cross section. (b) A metal-metal antifuse in a
three-level metal process.
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Quicklogic Metal-Metal Antifuse Resistance
Figure 4.4 Distribution of resistance values for
the QuickLogic metal-metal antifuse.
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Configuration via Static RAM

• Configuration data is loaded into static RAM on
  chip
• Static RAM cells control pass transistors which
  configure the logic cells and interconnect
• FPGA can easily be reconfigured, even on the fly
• Power must be maintained to the chip to retain
  the configuration or the configuration can be
  loaded from a PROM on power-up (usually serially)

Figure 4.5 The Xilinx SRAM configuration cell.
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EPROM Cell

• Used in EPLD devices and configuration EPROMS

Figure 4.6 An EPROM transistor. (a) With a high
programming voltage (gt 12V) applied to the drain,
electrons gain enough energy to jump onto the
floating gate. (b) Electrons stuck on gate 1
raise the threshold voltage so that the
transistor is always off for normal operating
conditions. (c) UV light provides enough energy
to the stuck electrons on gate 1 for them to
jump back to the bulk.
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Using FPGAs

• Changing demands from large FPGA users can often
  result in supply problems
• This is less of a problem in MGA or CBIC ASICs as
  this is arranged directly between the customer
  and foundry - although a shortage in ASIC foundry
  capacity is predicted in the future
• Most FPGAs are intended for direct placement into
  a PCB and are thus surface mount devices
• Unlike standard PLD devices (e.g. 22V10), FPGA
  signal and power pinouts vary widely among
  vendors
• Replacing an FPGA with an MGA or CBIC can be
  difficult because of this and may require pin or
  I/O locking

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Using FPGAs (cont.)

• Equivalent FPGAs available from different vendors
  or even from a single vendor may run faster than
  expected which can cause a problem for
  asynchronous designs
• For a given design, there can be a large
  performance difference between different FPGA
  architectures resulting from differences in the
  type and mix of logic
• Designers should be careful in choosing a given
  FPGA to implement their design
• Each type of FPGA (e.g. Actel 1020A) is available
  in a variety of configurations for packaging,
  grade (commercial or military), speed, and
  quantity
• Pricing is calculated using a base device price
  and a series of adjustment factors

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Actel FPGA Pricing Example