4 to 1 Multiplexer

1
4 to 1 Multiplexer
ELE 863 VLSI Systems

• Created by Charles Wong and Andre Savoie

2
Overview

• Introduction
• Theory
• Circuit performance issues
• Analysis
• Results
• Conclusion
• Acknowledgements
• References

3
Introduction

• CMOS is currently the most widely used method of
  circuit design
• Microscopic in size and consumes very low power
  thus more processing capability
• Examples are microprocessors, microcontrollers,
  static RAM

4
Theory

• A multiplexer is often known as a MUX
• It allows multiple data streams to propagate on a
  single line thus saving cost and space
• Ideal for uses in integrating voice and data
  transmission lines, network access to multiple
  data
• Consists of a number of data inputs, with one or
  more select inputs, and an output

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Theory (Continued)

• Passes the appropriate input signal to the output
  depending on the selected inputs

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Performance issues

• In any circuit dealing with logic gates, there
  are various delays present in the signals path
• Effort delay arises from the dimension of the
  gate as well as its internal configuration.
  Parasitic delay is also a problem dependent on
  gate sizing

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Performance issues (Continued)

• Circuits must be fabricated under existing
  conventions and practices
• Integrated circuits (ICs) are often assembled in
  a common package that is standardized
• They are often placed in small outline packages
  (SOPs) or dual in-line packages (DIPs) for easy
  connectivity

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Performance issues (Continued)

• Bond wires and bond pads are used to connect the
  circuit to its outside connection terminals
• They introduce inductance which slows down the
  response of the circuit by preventing sudden
  changes in trace currents

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Performance issues (Continued)
Bond pad/wire diagram (Fei Yuan. ELE 863 SSN
lecture notes. Toronto. 2006)
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Performance issues (Continued)

• The socket (test fixture or permanent connector)
  also must be modeled and simulated as it too
  offers impedance to signals propagating through
  the device
• Its conducting pins and traces also exhibit
  capacitance with one another

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Analysis
4 to 1 Multiplexer schematic with its truth table
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Analysis (Continued)

• Appropriate widths for the transistors needed to
  be determined in order to reduce the propagation
  delay while achieving equal falling and rising
  times at the output by using the following
  equation

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Analysis (Continued)
PMOS width 1.6µm NMOS width 0.8µm PMOS
width 4.616µm NMOS width 6.924µm PMOS width
11.095µm NMOS width 22.190µm
All lengths are a constant value of 0.35µm
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Analysis (Continued)

• With its current arrangement, the multiplexer is
  unable to drive certain loads because of the
  numerous stages the signal faces
• It is also vulnerable to harmful electrostatic
  discharge strikes
• To overcome these problems, a buffer was
  introduced at the output and ESD protection
  circuits were installed

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Analysis (Continued)

• For the buffer, transistor sizes were selected in
  an increasing fashion in order to provide decent
  driving current while maintaining minimal delay
• As for the ESD protection circuit, its main goal
  is to divert very large charges away from
  sensitive CMOS circuits where they could
  potentially be destructive

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Analysis (Continued)

• The primary branch is always made larger to
  absorb the bulk of the discharge current while
  the secondary stage is sized smaller because of
  its fast response time

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Results

• All simulations shown in the plots were performed
  at an input operating frequency of 62.5 MHz
• The select inputs were operating at a slower
  frequency of 10 MHz
• Considering rising and falling delays between
  input and output, an average overall delay was
  found to be 0.82ns without the package

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Results (Continued)

• When considering the package, the same test
  yielded an average overall delay of 1.00ns (an
  increase of approximately 20)
• Due to the ESD protection circuit, with a 2kV
  initial voltage across a capacitance of 100pF and
  a serial resistance of 1.5kO (approximations of a
  typical human body), the circuit was never
  introduced to a voltage higher than 4.9V

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Results (Continued)
Sample plot of MUX response without package (X0)
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Results (Continued)
Sample plot of MUX response with package (X0)
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Results (Continued)
ESD response plot (Voltage vs. time)
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Results (Continued)

• The multiplexer was introduced to capacitances
  varying from 10fF to 100pF but only performed
  well up to 10pF
• As for the response to temperature, the circuit
  was able to operate flawlessly in temperatures
  ranging from -60C all the way to 200C

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Results (Continued)
MUX response to varying output loads
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Results (Continued)
MUX response to varying ambient temperatures
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Conclusion

• The abovementioned topics have allowed for a
  better understanding of the workings of a 4 to 1
  multiplexer
• With such an exhaustive study of the system, all
  grounds were covered and any related exercise
  performed in the future may then be approached
  with greater insight and preparation

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Acknowledgements

• We would like to acknowledge Dr. Fei Yuan for his
  continuous assistance throughout the course of
  this undertaking

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References

• Brown, Steven Zvonko, Vranesic. Fundamentals
  of Digital Logic with VHDL Design. The
  McGrawhill Companies, Inc. United States of
  America. 2000
• Held, Gilbert. The Multiplexer Reference Manual.
  John Wiley and Sons Ltd. West Sussex, England.
  1992
• Weste, Neil H.E. Harris, David. CMOS VLSI
  Design A System and Circuits Perspective.
  Pearson Education, Inc. 2005