Radiation Hard Design Research

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Radiation Hard Design Research

• Wickham Chen
• July 25th 2005

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Problem definition

• How to create integrated circuits that are
  tolerant to high doses of radiation.

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Solutions

• Use a hardened SoS process along with special
  design techniques.

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Radiation effects

• Radiation creates electron hole pairs.
• Electrons are mobile and typically swept out of
  the oxide at high speed.
• Holes however are less mobile.
• Some will recombine with electrons
• Usually a large amount are trapped inside the
  oxide.
• The positive charge holes are responsible for
  changes in device properties.
• Total Dose
• Result from the interaction of ionising radiation
  with MOS device materials.
• Creates defects mainly in the gate oxide and
  oxide used for device isolation
• Single Event Effects
• Come from the interaction of a single energy
  particle through the device.
• Single Event Upset, Single Event Latch up, Single
  Event Transient

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Review

• Mosfet Structures

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Total Dose Effects

• Change in threshold voltage.
• Degradation of propagation delay.
• Increase in leakage current.

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Change in Threshold voltage

• A smaller thickness of the oxide reduces the
  threshold shift range.
• No layout countermeasures can be applied to
  eliminate this threshold voltage shift.

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Degradation of propagation delay.

• Degradation of the mobility in channel
  conductance and transconductance which leads to a
  decrease in gain.
• No layout countermeasures can be applied to
  eliminate this threshold voltage shift.

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Increase in leakage current

• Back channel leakage current
• Trapped positive charge in the back channel
  causing device failure.
• Solutions to this that Ive found are by using a
  BUSFET structure.
• Asymmetrical Source/Drain junctions
• Shallow Source Disconnects back channel.
• However difficult to align source and implant
  mask to scaled gate length. Difficult to scale
  SOI channel thickness.
• UTSI silicon film is so thin therefore very
  tricky to make a well formed and effective body
  under source contact.

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Increase in leakage current

• Birds beak leakage current
• Cause by overlap between thick field oxide and
  the polysilicon gate. Thick oxide acts as a
  parasitic transistor, which can turn in ON mode
  after accumulating many positive charges.
• Fixed by using edgeless layout technique. Since
  such transistors laid out in this fashion make
  sure that no overlap will ever occur between
  field oxide and polysilicon and thus no channel
  edge leakage.

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Leakage
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Single Event Effects

• (SEL) Single Event Latchup
• (SEU) Single Event Upset
• (SET) Single Event Transient

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Definition of SEL

• Single event latch up is the most destructive of
  the single event effects.

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Definition of SEL

• Single Event Latchup (SEL) is a potentially
  destructive condition involving parasitic circuit
  elements forming a silicon controlled rectifier
  (SCR). In traditional SEL, the device current
  may destroy the device if not current limited and
  removed "in time." A "microlatch" is a subset of
  SEL where the device current remains below the
  maximum specified for the device. A removal of
  power to the device is required in all
  non-catastrophic SEL conditions in order to
  recover device operations.

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How to design against SEL

• The use of guard rings
• Use of a process which does not allow this
  silicon interface to form. For instance, SoS
  technology.

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SEL solutions

• Guard Rings

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SEL solutions

• SoS process. No silicon substrate so no SCR can
  form. Also, guard rings are now unnecessary.

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Single Event Upset and Transient

• These effects can be minimized through the
  circuit design.

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Single Event Upset

• SEU
• A reversible change in digital logic state due to
  an energy particle passing through a device.

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Single Event Upset Solutions

• Resistive, capacitive and drive strength
  hardening.

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Hardening

• Resistive Hardening
• Introduction of extra resistors
• Capacitive Hardening
• Making sensitive nodes larger to increase
  critical charge.
• Ie. In a ELT use drain as outer ring instead of
  inner.
• Area penalty.
• Drive Strength
• Increase size of transistors to increase the
  drive strength of the sensitive node.
• Implies capacitive hardening since size increase.

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Layout countermeasures

• Enclosed layout
• Used by individuals at CERN
• Effective at suppressing edge leakage or birds
  beak leakage.
• Since such transistors laid out in this fashion
  make sure that no overlap will ever occur between
  field oxide and polysilicon and thus no channel
  edge leakage.

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Enclosed Layout
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Status

• Since Peregrines models are based on certain
  aspects of the mosfet being true doing an Annular
  Layout will be tricky.
• Talking with Peregrine we should find where the
  leakage is occurring the highest. If the back
  channel is where all the leakage is occurring
  annular geometry might not be feasible.
• Peregrine uses edge seal implants in the F
  process or .5 um to counter the edge leakage .
  Thus, no enclosed layouts are needed.
• They are suppose to send us some test chips
  already made for us to irradiate.

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Another process of Interest

• Silicon on Germanium
• SiGe HBT BICMOS
• Very High perfroamnce ie. 200GHz-300Ghz are
  acheiveable.
• Lower Power
• Implement with RHBD structures could be very
  promising.

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Idea of Collabration Occuring with Sige Process
for Space Applications