Task V

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Task V Overview of Three Dimensional Integration
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3-D Integrated Circuit
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Outline
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Motivation

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Motivation

• 3-D interconnects/device
• schemes are expected to reduce
• global wiring requirements
• significantly

• - Narrower interconnect length distribution,
  shorter semi-
• global and global interconnects
• - Smaller chip area, number of metallization
  levels per
• device layer, etc.
• 3-D system-on-a-chip
• - mixed signal/mixed technology based
  applications

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• Motivation
• Research goals
• - Technology development and characterization
• System-level performance modeling, technology
• assessment, and CAD tools development
• - Fabrication of a prototype 3-D IC
• Research accomplishment
• On-going and future work
• Summary

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Research Goals

• Development of 3-D technologies and
• integration schemes
• - Demonstration of test circuits using 3-D
  technologies
• Assessment of 3-D technology
• - Estimation of key performance metrics of 3-D
  ICs
• (chip area, clock frequency) and trade-off
  analysis
• - Evaluation of thermal issues in 3-D ICs

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Process Flow
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Process Flow
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Research Accomplishments
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Cu Bonding

• Cu-Ta sample bonded at 400oC
• for 30 min in bonding chamber
• Annealed at 400oC for 30 min in
• furnace (N2 purge)

• Lift-off or wet-etch Cu patterning

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Handle Wafer Etchback / Release

• Mechanical grindback until 100 mm Si remaining
• - Removal of remaining 100 mm Si using
  aqueous KOH / TMAH
• OR
• - Multiplexed SF6 / C4F8 etchback

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3-D Approaches
Wafer Bonding (MIT)
Seeding crystallization of ?-Si (Stanford)
Face-to-Face Bonding (RPI)
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Ni Seeded Lateral Crystallization

• Initially fabricate amorphous device
• Ni seeding for simultaneous crystallization and
  dopant activation
• Low thermal budget (Tmax lt 500ºC)
• Devices on top of a metal line
• MOSFETs
• Optical detectors

NMOS
PMOS
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3D Wafer-Stacking
Via
Via
Second Level (Thinned Substrate)
Device Surface
Bond
First Level
Device Surface
(a) face-to-face (b)
face-to-back

• Shorten long wires
• Small via (high aspect ratio)

• Enhance Performance
• Increase Functionality

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The Glue-Layer Approach to Wafer Bonding
1. Spin-on polymer (SOP) on both
wafers 2. Backside rinse and edge bead
removal 3. Bake to release solvent 4. Bake for
reflow 5. Align and bond wafers (in
vacuum) 6. Cure at cure temperature
Si Wafer
SOP SEAM
1 ?m
Si Wafer
J. F. McDonald, R. Kraft, J.-Q. Lu, A. Kumar, T.
Cale, T.-M. Lu, P. Belemjian, O. Ergodan, Y.
Kwon, A. Kaloyeros, and J. Castracane, Face to
Face Wafer Bonding for 3D Chip Stack Fabrication
to Shorten Wire Lengths, in 17th International
VLSI Multilevel Interconnection (VMIC)
Conference, pp. 90-95, Santa Clara, CA, June, 2000
FIB image shows clean interface (between Si
SOP) without voids. No interface between SOPs
observable
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High Aspect Ratio Processing
Trench Etching Capability
Develop and optimize electrically reliable,
structurally robust, fully- integrated etch,
liner, and fill processes for very high aspect
ratio structures. Solutions are compatible with
200-mm wafer semiconductor fabrication flows.
Via Concept
Liner Fill Capability
Passivation
Via Fill Capability
Cu Plug
Top metal connection
Wafer bonding interface
100nm
Bottom metal connection
100nm
CVD TaNx
CVD Cu
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Research Goals

• Development of 3-D technologies and
• integration schemes
• - Demonstration of test circuits using 3-D
  technologies
• Assessment of 3-D technology
• - Estimation of key performance metrics of 3-D
  ICs
• (chip area, clock frequency) and trade-off
  analysis
• - Evaluation of thermal issues in 3-D ICs

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Research Accomplishments
System-level modeling System-level modeling
for 3-D integration of microprocessors -
estimation of chip area, clock frequency,
interconnect parameters, via-density, and
number of repeaters Thermal analysis of 3-D ICs
and relevant packaging technology
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Modeling Framework
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Key Performance Metrics Estimation for
Microprocessors
3-D Implementation I
3-D Implementation II
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3-D Implementation I
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3-D Implementation II
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2-D and 3-D Wire-Length Distribution (logic
section)
Gate Pitch Normalized separation between
adjacent logic gates
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Comparison of Total Wire-Length
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Implication of shorter total wire-length and
fewer global wires in 3-D integration in a wiring
limited chip

• For fixed wiring pitch, smaller total chip area
• For fixed chip area
• - shorter interconnects smaller delay
• - larger interconnect pitch smaller delay
• - larger interconnect separation less
  cross talk
• Fewer repeaters

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Total Chip Area in 2-D and 3-D Implementation of
Microprocessors
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Delay of Scaled 3D ICs with 2 Si Layers

• Moving repeaters to upper active tiers reduces
  interconnect delay by 9.
• 3D (2 Si layers) shows significant delay
  reduction (63).
• Increasing the number of metal levels in 3D
  improves interconnect delay by another 40.
• Increasing the number of Si layers to 5 further
  improves interconnect delay.

Simulations assumed state-of-the-art chip at a
technology node with data from ITRS
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More than 2 Active Layers
Microprocessor Example from ITRS 50 nm
Node Number of Gates 269 million Minimum
Feature Size 50 nm Number of wiring levels,
9 Metal Resistivity, Copper 1.673e-6
Ohm-cm Dielectric Constant, Polymer 1.5
Normalized Interconnect Delay

• Initially the delay reduces rapidly
• As the number of active layers is increased the
  area required by vertical interconnects becomes
  appreciable.

No. of Active Layers
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Thermal Issues in 3-D Integration

• Estimation of total power dissipation and die
• temperature
• Thermal engineering to minimize die
• temperature
• Assessment of reliability issues in 3-D ICs

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Opportunities for lowering power dissipation in
3-D ICs by reducing the total capacitance of
- interconnect network - clock wiring and
clock drivers - logic gates (using bulk
and SOI-based devices)
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3-D IC Thermal Management SOLUTIONS
Near-Term Strategy Backside Bonding
of Microchannel Heat Sinks
Radical Long-Term Strategy Chip-Integrated
Channels
Glass
Convective heat removal by integrated
channels within and at the surface of the chip
Silicon
Close-up of 60 µmmicrochannel
Deliverable 200 W from 2 x 2 cm Closed-Loop
System with Electrokinetic Pump
PI Goodson, Stanford Tech Transfer
Intel Leveraged Funding DARPA
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Circuit-Level Reliability Assessment
Task Create ERNI3D based on ERNI (ERNI
Electromigration Resistance of Networked
Interconnect)

• Introduce 3-D trees
• Develop 3-D tree reliability model
• Develop bond reliability model
• Develop methodology for experimental
• characterization of bond reliability
• Include thermal models

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Task Develop Processes for Through-Wafer Vias

• Through- Wafer Cu-Filled Vias for
• gt2 device layers
• Chip-to-chip connections
• Thermal management

• New Research Electro-deposition
• System In-Place
• Filling of 10-to-1 aspect ratio
• demonstrated
• Coupled with thermal management
• analyses

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• Motivation
• Research goals
• - Technology development and characterization
• System-level performance modeling, technology
• assessment, and CAD tools development
• - Fabrication of a prototype 3-D IC
• Research accomplishment
• On-going and future work
• Summary

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On-Going/Future Work

• Technology
• Development and characterization of reliable
• 3-D integration technologies
• Design and fabrication of simple 3-D test
• circuit (e.g., ring oscillators) to demonstrate
  
• feasibility

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On-Going/Future Work

• Simulation and Modeling
• 3-D architecture and design methodology
• to minimize power dissipation and die
• temperature
• Assessment and modeling of signal integrity
• in 3-D ICs for mixed signal/SOC applications
• Development of CAD tools for 3-D ICs

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Summary

• Technology Development
• Explored key technological challenges of various
  
• 3-D schemes
• Technology Assessment
• Performed system-level modeling and trade-off
• analysis