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Memory

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Title: Memory


1
Memory and Programmable Logic
2
Memory
  • Memory Unit A collection of storage cells
    together with associated
  • circuits needed to transfer information in and
    out of the device.
  • Random-Access Memory (RAM)
  • Read-Only Memory (ROM)
  • Programmable Logic Device (PLD)
  • Programmable Logic Array (PLA)
  • Programmable Array Logic (PAL)
  • Field Programmable Gate Array (FPGA)
  • Erasable Programmable Read Only Memory (EPROM)

3
Random Access Memory
  • A memory unit is a collection of storage cells
    together with associated circuits needed to
    transfer information in and out of the device.
  • Stores binary information in groups of bits
    called words.
  • Word An entity of bits can be 16, 32, or 64.
  • 2-byte word, 4-byte word, 8-byte word
  • Byte Eight bits.

1
1
1
0
1
1
1
0
4
Memory Unit
n data input lines
k address lines
2k Words n bits per word
Read Write
n data output lines
5
Memory Unit Example
4 data input lines
4 address lines
24 Words 4 bits per word
Read Write
4 data output lines
6
Memory Unit Example
4 data input lines
  • 0 1 0 1
  • 0 0 1 0
  • 0 1 0 1
  • 1 0 1 1
  • 0 1 0 1

4 address lines
Read Write
4 data output lines
7
Memory Unit Example
4 data input lines
4 address lines
24 Words 4 bits per word
Read Write
1
1
1
0
4-bit word (half-byte, nibble)
4 data output lines
  • Memory units are specified by the number of
    words they contain, and the number of bits in
    each word
  • Each word has an address, starting from 0 up to
    2k 1, where the number of address lines is k.
  • The selection of a specific word in memory is
    done by applying the address to the address lines
  • The address is decoded and data at that address
    is made available at the output

8
Memory Unit Example
n data input lines
k address lines
K Kilobytes 210 bytes M Megabytes 220
bytes G Gigabytes 230 bytes A memory
unit has a capacity of 1K with 16 bits each.
What is the size of this memory unit?
2k Words n bits per word
Read Write
n data output lines
9
Memory Unit Example
n data input lines
k address lines
K Kilobytes 210 bytes M Megabytes 220
bytes G Gigabytes 230 bytes A memory
unit has a capacity of 1K with 16 bits each.
What is the size of this memory unit? 2K
2k Words n bits per word
Read Write
n data output lines
10
Memory Unit Read and Write Operations
n data input lines
k address lines
2k Words n bits per word
Read Write
  • Write Cycle Transfer
  • data into memory
  • Apply the binary address of the desired word to
    the address lines
  • Apply the data bits that must be stored in memory
    to the data input lines
  • Activate the write input

n data output lines
11
Memory Unit Read and Write Operations
n data input lines
k address lines
2k Words n bits per word
Read Write
  • Read Cycle Transfer
  • data out of memory
  • Apply the binary address of the desired word to
    the address lines
  • Activate the read input

n data output lines
12
Timing Waveforms Write Cycle
Clock Memory Address Memory Enable Read/Write
Data Input
Address Valid
Data Valid
13
Timing Waveforms Read Cycle
Clock Memory Address Memory Enable Read/Write
Data Input
Address Valid
Data Valid
14
Types of Memory
  • SRAM Static Random Access Memory
  • Internal latches (FFs) that store the binary
    information
  • Valid as long as the power is applied to the
    unit
  • DRAM Dynamic Random Access Memory
  • Stores the binary information in the form of
    electric
  • charges on capacitors
  • Capacitors discharge with (very little!) time,
    and must be
  • refreshed periodically.

15
Error Detection A Simple Scheme
4 data input lines
Odd Parity Bit
  • 0 1 0 1 1
  • 0 0 1 0 0
  • 0 1 0 1 1
  • 1 0 1 1 0
  • 0 1 0 1 1

address lines
4 data output lines
16
Error Detection A Simple Scheme
4 data input lines
Even Parity Bit
  • 0 1 0 1 0
  • 0 0 1 0 1
  • 0 1 0 1 0
  • 1 0 1 1 1
  • 0 1 0 1 0

address lines
4 data output lines
17
Error Detection A Simple Scheme
4 data input lines
Even Parity Bit Doesnt match the data
  • 0 1 0 1 0
  • 0 0 1 0 1
  • 0 1 0 1 0
  • 1 0 1 1 1
  • 0 1 0 1 0

address lines
4 data output lines
18
Error Detection A Simple Scheme
4 data input lines
Problem Even Parity Bit DOES match the data
  • 0 1 0 1 0
  • 0 0 1 0 1
  • 0 1 0 1 0
  • 1 0 1 1 1
  • 0 1 0 1 0

address lines
4 data output lines
19
Error Detection A Simple Scheme
4 data input lines
Problem Parity Bit DOES match the data But
these dont
0 1 0 1 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0
1 0 1 0 1 1 0 0 0
address lines
4 data output lines
20
Even Parity Checker
Design a circuit to store the even parity of the
state of this register
1
1
1
0
4 data input lines
4 data output lines
21
Hamming Codes
n-bit data word k parity bits are added to it to
form a new word of nk bits Bit positions are
numbered from 1 to nk The positions numbered as
a power of 2 are reserved for parity bits The
remaining bits are the data bits Hamming Code
can be used with words of any length
22
Hamming Codes
Example 01011001 k parity bits are added to it
to form a new word of nk bits Bit Position 1
2 3 4 5 6 7 8 9 10 11
12 P1 P2 P3
P4 The positions numbered as
a power of 2 are reserved for parity bits The
remaining bits are the data bits
23
Hamming Codes
Example 01011001 Bit Position 1 2 3
4 5 6 7 8 9 10 11 12
P1 P2 0 P3 1 0
1 P4 1 0 0 1 P1 XOR of bits
3, 5, 7, 9, 11 P2 XOR of bits 3, 6, 7, 10,
11 P3 XOR of bits 5, 6, 7, 12 P4 XOR of bits
9, 10, 11, 12
24
Hamming Codes
Bit Position 1 2 3 4 5 6 7
8 9 10 11 12 P1
P2 0 P3 1 0 1 P4 1 0
0 1 P1 XOR of bits 3, 5, 7, 9, 11 P2
XOR of bits 3, 6, 7, 10, 11 P3 XOR of bits 5,
6, 7, 12 P4 XOR of bits 9, 10, 11, 12 Then
when the bits are read from memory they are
checked Using the following check bits C1
XOR of bits 1, 3, 5, 7, 9, 11 C2 XOR of bits 2,
3, 6, 7, 10, 11 C3 XOR of bits 4, 5, 6, 7,
12 C4 XOR of bits 8, 9, 10, 11, 12
25
Hamming Codes
Given the 8-bit data word 01011011 Generate the
13-bit composite word for the Hamming Code
that 1. Corrects single errors 2. Detects
double errors
26
Hamming Codes
Given the 8-bit data word 01011011 Generate the
13-bit composite word for the Hamming Code
that 1. Corrects single errors 2. Detects
double errors Bit Position 1 2 3 4
5 6 7 8 9 10 11 12
P1 P2 0 P3 1 0 1
P4 1 0 1 1 P1 XOR of bits 3,
5, 7, 9, 11 P2 XOR of bits 3, 6, 7, 10, 11 P3
XOR of bits 5, 6, 7, 12 P4 XOR of bits 9, 10,
11, 12
27
Hamming Codes
Given the 8-bit data word 01011011 Generate the
13-bit composite word for the Hamming Code
that 1. Corrects single errors 2. Detects
double errors Bit Position 1 2 3 4
5 6 7 8 9 10 11 12
0 0 0 1 1 0
1 1 1 0 1 1
28
Hamming Codes
Given the 8-bit data word 01011001 Generate the
13-bit composite word for the Hamming Code
that 1. Corrects single errors 2. Detects
double errors Bit Position 1 2 3 4
5 6 7 8 9 10 11 12 13
0 0 0 1 1 0 1 1
1 0 1 1 1
29
Memory
  • Programmable Logic Device (PLD) Allows us to
    fabricate a large circuit on
  • a single chip.
  • Programmable Logic Array (PLA) Has a
    programmable AND array and
  • a programmable OR array
  • Programmable Array Logic (PAL) Has a
    programmable AND array and
  • a programmable OR array
  • Programmable Read Only Memory (PROM) Has a
    fixed AND array and
  • a programmable OR array

30
Programmable Logic Devices
x
x
x
x
x
x
a b c d
a b c d
abcd
bd
31
Programmable Logic Devices
a b c d
a b c d
abcd
a b c d
a b c d
bd
32
ROM Truth Table
Inputs Outputs I3 I2 I1 I0 A3
A2 A1 A0 0 0 0 0 0 1 0 1 0
0 0 1 1 1 1 0 0 0 1
0 0 0 1 1 1 1 1
1 1 0 1 0
33
ROM Truth Table
Inputs Outputs I3 I2 I1 I0 A3
A2 A1 A0 0 0 0 0 0 1 0 1 0
0 0 1 1 1 1 0 0 0 1
0 0 0 1 1 1 1 1
1 1 0 1 0
Decoder
I3 I2 I1 I0
. . .
34
ROM Truth Table
Inputs Outputs I3 I2 I1
I0 A3 A2 A1 A0 0 0 0 0 0 1 0
1 0 0 0 1 1 1 1 0 0 0
1 0 0 0 1 1 1 1
1 1 1 0 1 0
Decoder
I3 I2 I1 I0
. . .
A3 A2 A1 A0
35
ROM Truth Table
Inputs Outputs I3 I2 I1
I0 A3 A2 A1 A0 0 0 0 0 0 1 0
1 0 0 0 1 1 1 1 0 0 0
1 0 0 0 1 1 1 1
1 1 1 0 1 0
Decoder
I3 I2 I1 I0
. . .
A3 A2 A1 A0
36
Programmable Logic Array
A
B
C
F1
AB
0
ABC
1
F2
BC
AB
C C B B A A
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