Router Design

1
Router Design Route Look Up in Backbone
Routers

• Muthuvelan KP
• email kpm_at_ittc.ku.edu
• website http//www.ittc.ku.edu/kpm/

2
Outline

• Introduction
• Router Architectures
• Route Lookup Mechanisms
• Conclusion

3
Introduction

• What are the functions of a router?
• Routing forwarding
• How is a core router differ form a normal router?
• More focus on forwarding QoS (classification,
  queuing, policing, rate-shaping )
• Fast path vs. Slow Path
• Key design issues with regard to core router
  design
• Performance (throughput latency)
• Reliability
• Scalability

4
First Generation Router Architecture
CPU
Shared Memory
Interface Card
Interface Card
Interface Card
5
Present Generation Router Architecture
Route Processor
Switch Fabric
Line Card
Line Card
Line Card
Line Card
Line Card
Line Card
6
Router Architectures

• General Issues
• Forwarding
• Mostly done in parallel in each line card.
• Parallelism through part replication
• Switching
• Queuing
• Scheduling

7
Queuing

• Input Queuing
• HOL (Head of Line) blocking
• Difficult to characterize QOS requirements
• Output Queuing
• Backplane speedup
• Virtual Output Queuing
• Multiple queues maintained at the input for each
  output port

8
HOL Blocking
Route Processor
Switch Fabric
Line Card
Line Card
Line Card
Line Card
blocked
Line Card
Line Card
9
Switching

• Shared Memory First Generation, PC
• Shared Bus Bus Arbitration Overhead
• Point-to-Point (or Crossbar) Commonly used

10
Scheduling

• FCFS
• Primitive, not fair
• Priority Queues
• Starvation
• Fair Queuing
• Round Robin, large packets have advantage
• Weighted Fair Queuing
• Rate based solution, commonly used

11
Route Lookup Algorithms
12
Route Lookup In Backbone Routers

• No. of routes enormous and increasing
• 100,000 routes
• High Links Speeds
• Approaching OC768 ( 40 Gbps )
• Optical-electrical mismatch
• Change in Lookup Mechanisms
• Before CIDR, no mask length
• After CIDR, variable mask length

13
Packet Processing on Data Path

• Receive packets on input interface
• Lookup on Packet Headers
• Switching across the routers
• Prepend new Header
• Send packets on output interfaces

14
Key Aspects of Route Lookup

• Number of memory access ( or search time )
• Incremental updates
• Memory requirements
• Two key categories
• Search by length trie
• Search by values array, hash

15
Classical Solution Binary Trie

• Binary Search
• Key IP Address, Result Next hop information
• Search Mechanism
• Remember the BMP (Best Match Prefix) so far
• Search ends when no branches
• Prefix search by length reduces search space by
  half
• No bit string stored in nodes
• Update Operation
• Insertion search insert nodes
• Deletion search unmark the prefix

16
Classical Solution Binary Trie

• Example, prefixes
• (a) 0
• (b) 11
• (c) 011
• (d) 0000
• (e) 0001

1
0
a
1
0
1
b
1
0
c
0
1
d
e
17
Path Compressed Tries

• Single-child branches are removed from the binary
  trie
• Prefix information stored in the nodes
• Search Mechanisms
• Compare only against certain bit positions
• Search ends when there is no branch or when there
  is a mismatch
• BSD tries
• No prefix matching while descending the trie
• Backtracking to the longest matching prefix

18
Path Compressed Tries
1

• Example, prefixes
• (a) 0
• (b) 11
• (c) 011
• (d) 0000
• (e) 0001

1
0
2
a
1
1
0
4
b
c
1
0
1
d
e
19
Advanced Techniques

• Prefix expansion
• Original prefixes
• 0 -gt a
• 01 -gt b
• After prefix expansion
• 00 ? a
• 01 -gt b
• 10 -gt a
• 11 -gt a

20
Advanced Techniques

• Disjoint prefixes
• Prefixes do not overlap ( i.e no prefix is itself
  a prefix of another prefix).
• A trie with disjoint prefixes will have prefixes
  at the leaves but not at internal nodes
• Can be obtained by adding leaves to nodes that
  have only one child and unmarking the internal
  nodes.
• Also known as leaf pushing.

21
Disjoint Prefixes

• Example, prefixes
• (a) 0
• (b) 11
• (c) 011
• (d) 0000
• (e) 0001

1
0
1
0
1
b
1
0
1
0
c
a
a
0
1
d
e
22
Multibit Tries

• Inspect multiple bits at the same time
• Stride number of bits inspected at a time
• Fixed stride vs. Variable Stride
• Cannot support arbitrary prefix lengths. Hence,
  prefix-expansion is done.
• Choice of stride
• Decides the number of memory access
• Can let the structure of the binary tree decide.
  Full binary sub trie can be replaced.

23
Multibit Tries

• Update Operations
• Each subtrie has a local BMP (Best Match Prefix)
• Insertion deletion are local to a sub tries
• Deletion has a problem
• set of longer prefixes could have overwritten a
  expanded prefixes
• The original prefixes have to be stored
  separately
• Memory Consumption
• High due to expansion storage of info in
  internal nodes.

24
Multibit Disjoint Tries

• Only leaves store information
• Less memory consumption
• Update operations takes longer time
• Updates not local to subtrie

25
Level Compressed(LC) Tries

• Multibit tries with path compression
• Variable stride trie
• Replace full binary trie with Multibit subtrie of
  stride k based on a fill factor x with 0ltx1

26
Level Compressed(LC)- Tries

• All the nodes are stored in a single array
  root, 1st level nodes, 2nd level nodes,..
• Leaves have a linear list of prefixes
• Lot of variations of the LC tries presently
  available

27
Binary Search on Prefix Length (Waldvogel)

• Hash Tables for prefixes of each length binary
  search.
• Markers used to guide search
• If lt match-foundgt goto higher length
• Else lt can goto lower or higher length prefixesgt
• Markers kind of false prefixes
• Example for 1111, markers would be 1, 11,
  111
• Issues
• Markers could mislead hence BMP is remembered
• Additional memory due to markers sparse
  distribution of prefixes

28
Complexity Comparison
N No. of Prefixes, W length of prefix
29
Hardware Approaches

• ASIC (Application Specific Integrated Circuits)
• CAM (Content Addressable Memory)

30
ASIC Based Solution

• Finer control over memory
• Access to small junks of memory for trie based
  lookup
• Pipeline (parallelism through part replication)

31
ASIC Based Solution

32
CAM Based Solution

• Content Addressable Memory
• Inverse of RAM does parallel search on contents
• RAM with logic circuit around it
• Types
• Binary CAM 0s 1s
• Ternary CAM 0s, 1s dont care bits

33
Binary CAM Algorithms

• Multiple Cycle, Single Logical CAM
• Single Cycle, Multiple Logical CAM
• Has prioritizer control logic

34
Ternary CAM Algorithms

• Single cycle, Single logical CAM
• Prefixes stored in a ordered way
• Update operations require total re-initialization
• Multiple cycle, Single logical CAM
• Store explicit priority along with prefix
• Search with lt prefix, prioritygt in CAM
• Binary search on priority log W.

35
Conclusion

• Is Route Lookup an Art or Science?
• Thank You!