Systematic Design of a 14bit 150MSs CMOS CurrentSteering DA Converter

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Systematic Design of a 14-bit 150-MS/s CMOS
Current-Steering D/A Converter

• Geert Van der Plas, Jan Vandenbussche, Walter
  Daems1, Anne Van den Bosch, Georges Gielen2,
  Michiel Steyaert, Willy Sansen

Katholieke Universiteit Leuven Department of
Electrical Engineering Division
ESAT-MICAS http//www.esat.kuleuven.ac.be/micas/ K
ardinaal Mercierlaan 94 B-3001 Heverlee BELGIUM
1 Research assistant of the Fund for Scientific
Research Vlaanderen (FWO-V) 2 Research
assiociate of the Fund for Scientific Resaerch
Vlaanderen (FWO-V)
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Overview

• Introduction
• Proposed flexible architecture
• Mixed Signal Design Methodology
• Design Example
• Measurement results
• Conclusions

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Introduction

• High-performance converters
• Video
• Telecommunications
• Wireless
• .

Specs SFDRLinearityUpdate ratePower Area
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High Performance Design
HighPerformanceDesign
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Overview

• Introduction
• Proposed flexible architecture
• Mixed Signal Design Methodology
• Design Example
• Measurement results
• Conclusions

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Architecture Operating Principle
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Block Diagram Floorplan

• Switching Sequence

• Switching Scheme

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Overview

• Introduction
• Proposed flexible architecture
• Mixed Signal Design Methodology
• Design Example
• Measurement results
• Conclusions

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Design Methodology Flow

• Performance driven
• Top-down
• Bottom up
• Supported by tools
• Matlab
• Logic synthesis tools
• Spice based optimization
• Mondriaan
• Standard cell tools

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Overview

• Introduction
• Proposed flexible architecture
• Mixed Signal Design Methodology
• Design Example
• Measurement results
• Conclusions

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Design Example Specifications

• 14 bit
• INL DNL lt 0.5 LSB
• gt 100 Msamples/s
• gt 84dB SFDR
• In standard 0.5m 1P3M CMOS technology
• Minimize power and area

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Design Overview

• Architectural Sizing
• Static performance
• Dynamic performance
• Analog Device level sizing
• Current source
• Switches and latch
• Layout Generation

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Static Performance

• Switching Scheme
• 1, 4 or 16 units ?
• reduces systematic errors of current sources

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Static Performance

• 14 bit D/A converter
• 16 units Quad Quadrant
• Estimate error profile Van der Plas ProRISC 99
• odd components are suppressed
• even components are reduced
• Extracted profile

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Static Performance

• Sequence ?
• 2m! Possibilities (m8 256!)
• Solution optimization process (min INL)
• Optimize the sequence of 16 4x4 regions
• Cycle through the regions and turn on one source
  of each region before returning to the same region

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Static performance result
Q2 Random Walk
Manual derived
INL 101
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Dynamic Performance

• Segmentation (l/m)
• Increasing m improves SFDR Bult ISSCC 98
• But increases area of decoder and routing

m8l6
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Design Overview

• Architectural Sizing
• Static performance
• Dynamic performance
• Analog Device level sizing
• Current source
• Switches and latch
• Layout Generation

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Current Source Sizing

• Random Errors Yield (INL lt 0.5LSB) gt 99

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Current Source Sizing
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Latch Sizing

• Synchronize signals
• Tune crossing point of switch signals
• Low glitch, optimal SFDR
• Spice based optimization

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Layout Generation

• Floorplanning
• Module Layout Generation
• Current source array
• Switch/latch array
• Decoder Standard cell place and route
• Layout assembly

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Floorplanning

• Area estimates of modules
• (Near) square chip
• Pitch of buses is calculated
• Elegant module assembly, connections by abutment
• Area optimization happens at this level

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Mondriaan

• Many regular structures
• Buses and trees
• Current source array
• Switch Latch array
• Dedicated tool Mondriaan CICC 98 Van der Plas
• Tree bus device generators
• Place and route for regular structures

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Layout of the 14-bit D/A Converter
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Measurement Setup
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Static Measurements
DNL lt 0.2 LSB
INL lt 0.3 LSB
DAC DNL LSB
DAC INL LSB
DAC Input code
DAC Input code
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Output Spectrum _at_ 500KHz
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Conclusions

• 14-bit 150 Msamples/s D/A Converter
• Systematic Design Methodology
• Mixed signal
• Performance driven
• Hierarchical
• Top down / bottom up
• Commercial and newly developed tools
• Sizing scripts optimization
• Mondriaan
• Total design effort 1 person-month

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Design D/A Converters that have ...

• High accuracy 10 bit and higher
• High speed 100 Msamples/s and higher
• Low power consumption and small area
• Short design time a few man-months
• in standard CMOS technologies
• Macrocell / Soft Cell ready

Flexible Architecture Systematic Design
Methodology
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Architectural Sizing

• Static Performance
• Random errors mismatch
• Systematic errors
• Process gradients
• Temperature gradients
• Electrical gradients
• Edge effects
• Supply line voltage drops
• Dynamic Performance
• Segmentation l/m

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Device level synthesis

• Current source
• Static performance INL DNL
• Yield
• Full scale current
• Switch latch
• Dynamic performance SFDR

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Overview

• Introduction
• Proposed flexible architecture
• Mixed Signal Design Methodology
• Design Example
• Measurement results
• Conclusions