Boosters for Driving Long Onchip Interconnects: Design Issues, Interconnect Synthesis and Comparison

1
Boosters for Driving Long On-chip
Interconnects Design Issues, Interconnect
Synthesis and Comparison with Repeaters

• Ankireddy Nalamalpu
• Intel Corporation/Hillsboro
• Wayne Burleson
• UMASS/Amherst
• Partially Funded by SRC under research ID 766

2
Motivation

• Interconnect delay will dominate DSM
• Limited performance by using traditional
  techniques (Repeaters) for driving on-chip
  interconnects
• Repeaters are area and power hungry
• This study aims to provide
• New high-performance circuit technique (Booster)
  for driving interconnects
• Over-all Booster design methodology to integrate
  into automatic interconnect synthesis tools
• Study/comparison Boosters with Repeaters

3
Repeater Design

• Classical delay optimal repeater solution when
  delay of repeaters equals interconnect delay
  Bakoglu85
• Repeater design solutions model short-channel
  effects in DSM using Alpha Power MOSFET model
  Friedman98b, Nalamalpu00b

4
Repeater Design Limitations
60
6x106
50
5x106
Repeaters
40
4x106
Plot from Sylvester99
Power(W)
30
Repeaters Wire
of Repeaters
3x106
20
2x106
10
Wires Only
1x106
0
0.25
0.2
0.15
0.1
0.05
Technology Generation(?m)

• Limited performance with Repeaters in DSM due to
  non-negligible interconnect resistance
• Increasing Repeater Area and Power with
  technology scaling Sylvester98, Sylvester99
• 700,000 repeaters in 70nm CMOS Cong99
• Increased design problems with repeaters driving
  bi-directional and multi-source buses
• Inverting Polarity

5
Review of Previous Work
Driver
Driver
Interconnect
Interconnect
2,4Inverters
Receiver
Receiver

• Regenerative Feed-back Repeaters for driving
  programmable interconnectionsDobbelaere95
• Extremely sensitive to Noise
• Meta-stability
• Two-sided Timing Constraints
• Limit in performance gain

6
Review of Previous Work

• Differential, Small-swing and other design
  techniquesLima95,Friedman98a
• Requires more circuit design sophistication
• Cumbersome for automatic interconnect synthesis
  tools
• Require multiple Power Supplys in some cases
• We need simple and yet high-performance circuit
  technique that can be integrated into automatic
  interconnect synthesis tools

7
Proposed Design

• Our proposed circuit (Booster) differs from the
  existing designs in one or more of the following
• High Performance
• Simpler and requires fewer transistors
• Noise immunity
• Eliminates Meta-stability
• We formulate analytical design rules for Boosters
  to be part of automatic interconnect synthesis
  tool

8
Booster Circuit
9
Booster Simulations

• RLC 5 T-Interconnect model in 0.16?m CMOS
• Feedback path
• Improves the speed of driver
• Prevents turning-off booster prematurely thereby
  eliminating two-sided timing constraints
• Makes circuit glitch immune

Input
Firing
Feed-back Path
Inverter Outputs
10
Booster Design

• Skewed inverters respond to opposite ends of
  voltage transition
• Driving both the inverters to feed-back path
  improves noise immunity
• Full keeper helps noise cause
• Booster firing time depends on switching
  thresholds of inverters
• Boosters attach to the wire rather than
  interrupting it so can be used for bi-directional
  signals
• Boosters dont impact the polarity of the signal

11
Booster Design Methodology

• Analytically determine number of boosters and
  their placements for driving given interconnect
  load
• Consider only delay optimality
• Minimize power/area impact without losing
  significant speed-up

12
Booster Placement
350
Delay without Booster(ps)
300
250
200
150
Delay with Booster(ps)
BR1
BR2
BR3
100
50
BR1, BR2, BR3 Boosters
0.5
2.0
3.0
1.5
1.0
2.5
Booster Transient Variation(t/T)

• Boosters no good for driving very short wires due
  to fast transients in small RC loads (how short?)
• In-order to place a booster
• Firing time(T) lt Time Constant(t)
• Booster Transient variation (t/T) gt 2.5, to
  minimize total number of boosters

13
Booster Analytical Model
Node(a)
Node(b)
bp
tn
Length L3
Length L2
Length L1

• Using simple inverter model(which will suffice)

14
Booster Analytical Model

• Using more accurate alpha-power law based
  inverter analytical model Nalamalpu00b
• Alpha power MOSFET law Sakurai90 models
  short-channel effects
• Repeater model is within 5 error of SPICE

15
Rule for Number of Boosters
Interconnect Delay
Short-circuit Power
Number of Boosters

• When boosters(BR1, BR2, BR3) are initially off
• L1,L2 and L3 will be different for identical
  segment delays due to characteristics of signal
  propagation along RC line
• Unlike Repeaters, placing non-optimal number of
  boosters doesnt impact performance as much as
  power

16
Rule for Number of Boosters
L1
L2
L3
L4
BR1
BR2
BR3
BR4
BR1, BR2, BR3, BR4 Boosters

• To Minimize number of boosters
• Any down stream booster (e.g.BR2) should be
  fired only after improved upstream signal
  transient (e.g. A, BR1 is active) propagates
  downstream (e.g.B)
• L1ltL2ltL3ltL4 for identical segment delays

17
Booster Placement Sensitivity
Block A
Block B
Block C
No Glue Logic

• Realistic floor-plans will have several
  placement constraints
• Inter block routing
• Repeater staggering to reduce inductive and
  capacitive coupling
• To ensure the design is manageable (e.g.
  verifiable, reusable)
• To maintain datapaths regularity

18
Booster Placement Sensitivity

• Repeaters are shown to be sensitive to placement
  variationNalamalpu00a
• Worst case placement scenarios results in
  performance degradation by as much as 30
• Boosters relatively insensitive to placement
  variation due to its dependence on transient

19
SPICE Simulations

• We used delay optimal repeater design solution
  obtained by using alpha-power MOSFET
  modelNalamalpu00b
• Booster design rules for finding number of
  boosters and their placements are used to
  minimize design cost without losing significant
  speed (lt5)
• CMOS 0.16 ?m process is used for SPICE
  simulations
• Interconnect load is represented using RLC 5
  T-model

20
SPICE Simulations
nbooster
nrepeater
Dbooster
Drepeater
Wbooster
Wrepeater
(?m)
(?m)
(ps)
(ps)
21
Boosters Vs Repeaters

• Boosters shown to out-perform Repeaters by 20
  for all kinds of interconnect loads (both
  capacitive and resistive dominated)
• Boosters interconnect driving distance is 3x that
  of Repeaters resulting in fewer Boosters
• Significant reduction in Area over Repeaters
  (more than 100 depending on interconnect load)
• Boosters are insensitive to placement variation
• Boosters dont impact the polarity of the signal

22
Booster Applications

• Uni/bi-directional interconnects
• Multi-source/sink buses
• Programmable Interconnections in FPGAs

Booster
Off Switches
On Switches
Booster
Booster
Booster
23
Booster Applications

• Long AND domino gates (e.g decoders)
• Precharge from top of the stack and discharge is
  from bottom of the stack
• Bi-directional signaling can be improved using
  boosters

24
Booster Limitations

• Boosters dont break lines however for buffering,
  modularity and signal integrity reasons it is
  desirable to break long lines
• Boosters are not well understood by CAD tools and
  designers

25
Conclusions

• We presented analytical design solutions, both
  hard optimization and softer realistic design
  problems
• We propose to combine Boosters with Repeaters in
  some cases to handle both modularity and signal
  integrity issues
• Boosters find application in long dynamic ANDs,
  and multi-source interconnects in addition to
  conventional point-to-point long lines

26
Future Work

• Integration into interconnect synthesis tool with
  Repeaters
• Impact on bi-directional multi-source lines which
  could directly impact VLIW, FPGA, Routers,
  multi-processor, memory and other highly
  connected architectures

27
Acknowledgements

• Sriram Srinivasan for insightful comments
• Prof. Arnold Rosenberg for the initial
  theoretical motivations in exploring booster
  circuits
• SRC for partially supporting under Research ID
  766
• UMASS has filed for several patents related to
  Booster technology

28
References

• Dobbelaere95 Dobbelaere et al , Regenerative
  Feed-back Repeaters for Programmable
  Interconnections, JSSC, 1995
• Lima95 T. Lima et al, Capacitance Coupling
  Immune Accelerator for Resistive Interconnects,
  IEEE Trans. on Electron Devices, 1995
• Friedman98a Secareanu et al, Transparent
  Repeaters, GLSVLSI,1998
• Nalamalpu00a A. Nalamalpu et al, Quantifying
  and Mitigating Placement Constraints, 2000
• Sakurai90 Sakurai et al , Alpha-Power MOSFET
  Model, JSSC,1990
• Nalamalpu00b A. Nalamalpu et al , Repeater Ramp
  based Analytical Model, ISCAS,2000

29
References

• Sylvester98 D.Sylvester et al, Getting to the
  bottom of deep sub-micron, ICCAD, 1998
• Sylvester99 D.Sylvester et al, Getting to the
  bottom of deep sub-micron II, ISPD, 1999
• Friedman98b V.Adler et al, Repeater Design to
  Reduce Delay and Power, IEEE Trans. Circuits and
  System II, 1998
• Bakoglu85 Bakoglu et al, Optimal
  Interconnection Circuits for VLSI, IEEE Trans.
  Electron Devices, 1985