Part B : Integration of SSP with ARM system using a SoC bus

1

• VLSI1/EE360R
• Laboratory Exercise 3

2
Overview

• RTL level system design using Verilog (Behavioral
  Modeling)
• Part A Synchronous Serial Port (SSP)
• Part B Integration of SSP with ARM system using
  a SoC bus interface called Wishbone
• Tools
• Simulation VCS, Virsim
• Synthesis Design Vision

3
Overview RTL design with Verilog
Vcs/ virsim

• Verilog
• A hardware description lang.
• Structural description
• Behavioral description
• Synthesizable code

RTL level
lab3
Design Analyzer (Synthesis tool)
Gate level
Virtuoso editor
lab2
SE (APR tool)
Tr. level
lab1
Virtuoso editor
Layout
4
System Overview given system
ARM RISC, 4 stage pipelined, LD/ST
architecture
5
System Overview new system
6
Specifications - SSP

• Block Diagram of SSP

7
Specifications - SSP

• Transmit FIFO (TxFIFO), Receive FIFO (RxFIFO)
• 8-bit wide, 4-locations deep FIFO
• Only valid data need to be buffered
• FIFO full generates SSPTXINTR signal
• Transmit and receive logic
• Performs parallel-to-serial and
  serial-to-parallel conversion
• Transfer (or receive) data synchronously

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Specifications - SSP

• Signal Description
• CLEAR_B Low active clear signal
• SSPCLKIN, SSPCLKOUT
• Synchronization clock for data transfer
• 2 times slower than PCLK
• PSEL chip select signal for SSP
• PWRITE 1 Write, 0 Read
• SSPFSSIN, SSPFSSOUT indicates starting of data
  transfer
• SSPOE_B Low active output enable signal,
  indicates when SSPTXD is valid
• Assume perfect synchronization between SSPCLKIN
  and SSPCLKOUT testing is done with external
  loop back

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Specifications SSP Timing Diagram

• Frame format

10
Specifications SSP Timing Diagram

• Frame Format (continuous transfer)

11
Module design and simulation
test_module.v

• Procedure
• Design a module (module.v)
• Make a testbench file (test_module.v)
• - can be recycled for other modules after
  small modification
• Make a makefile (make_module)
• - simple list of verilog files to compile
• Run simulation
• (vcs RI Mupdate f make_module)

provide input data/signals
module.v
Observe output data/signals
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Specifications - WISHBONE

• Activities need to be supported
• Instruction Read
• When ARM accesses h0000000-h000FFFF
• Generates memory access signals
• Deliver instructions from memory to ARM
• Mem-Slave-Master-ARM
• Data Read
• When ARM accesses h0010001
• Generate SSP access signals
• Deliver data from SSP to ARM
• SSP-Slave-Master-ARM

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Specifications - WISHBONE

• Activities (continued)
• Data Write
• When ARM accesses h0010000
• Generate SSP access signals
• Deliver data from ARM to SSP
• ARM-Master-Slave-SSP
• Interrupt handling
• Stop ARM by holding phi1 and phi2
• e.g. SSP Overflow Interrupt
• SSP-Slave-Master (holds clocks)

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Handshaking signals for data communication
data_out
data_in
load
stb
ack_o
ack_i
reset
clock
data_in
data_in
data_out
data_out
stb
stb
load
load
ack_o
ack_i
ack_o
ack_i
reset
reset
clock
clock
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Handshaking signals (ctnd.)
Preferable Timing Scheme for (latching,
outputting) of a module and their serial
connection 1. (pos in, pos out) 2. (pos
in, neg out) This avoids depending on skew
matching for proper data transfer.
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Simulation of whole system

• Write your own assembly test program using ARM
  instructions.
• Refer ARM manual given to you.
• Compile the program and save it to
  /images/mem.data (- actual memory image)
• asm_arm myprogram mem.data
• Template mem.data is given for testing you may
• choose to create your own
• Run VCS/Virsim
• Makefile for TOP module

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Integration Tip

• Phi1 and phi2 should be non-overlapping clocks
  (their edges should be non-overlapping).
• Check the functionality and synthesizability of
  your sub-module frequently.
• You can check if your module is synthesizable by
  reading it from Design Analyzer (should have no
  error when read).

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Synthesis (new modules only)

• Using Design Vision
• Code should be synthesizable
• (i.e. readable from Design Vision without
  error messages)
• Library has no flops with async reset use
  synchronous reset if you need to clear flop
  contents
• Observe area/timing trade off
• First, run without constraint (initial run)
• - you can get initial area and initial
  arrival time
• Run with area optimization option with smaller
  area than initial area
• Run with timing optimization option with smaller
  clock period than initial arrival time

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Example of designing a module

• This example illustrates handshaking
• The module latches the incoming data_in (into an
  internal register) at the positive edge of the
  clk when the load signal is high
• It sends out this data (to data_out) and asserts
  the
• stb high for one cycle if it receives an ack_i
  (acknowledge) input from the other module at the
  negative edge of the clk.
• So load, ack_i and stb are the handshaking
  signals
• A synchronous reset initializes all internal
  states to 0
• Ports reset, clk,
• load, ack_i, stb
• data_in, data_out

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Code

• Declare the module
• module module8 (clear, clk, load, data_in,
  ack_i, data_out, stb)
• Inputs/outputs/registers declaration
• input reset, clk, load, ack_i
• input 70 data_in
• output stb
• output 70 data_out
• reg stb //we will need to assign
  and store a logic value
• reg 70 in_buf //internal register
• reg 70 data_out

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Code contd.

• The module latches the incoming data (into an
  internal register) at the positive edge of the
  clock when the load signal is high
• always _at_(posedge clk) begin
• if (reset)
• in_buf
• else
• if (load)
• in_buf
• end

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Code contd.

• always _at_(negedge clk) begin
• if (reset) begin
• stb
• data_out
• end
• else
• begin
• if (ack_i) begin
• //check the handshaking signal from the module
  who receive our output
• stb
• //sending out the handshaking signal to the
  receiving module.
• data_out
• end
• else if (stb 1'b1)
• stb
• end
• end

23
Testbench

• Declare testbench
• module module8_test
• Declare Registers
• reg clock, reset, ld, ack_i
• reg 70 din
• wire stb
• wire 70 dout

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Testbench contd.

• It sends out this data (to data_out) if it
  receives an ack_i (acknowledge) input from the
  other module at the negative edge of the clock
• initial begin
• clock 0
• reset 1
• ld 0
• ack_i 0
• 35 reset 0
• 15 din 8'b10100011
• ld 1
• 40 ld 0
• 75 ack_i 1
• 40 ack_i 0
• end

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Testbench contd.

• Clock
• always
• 20 clock clock
• Declare the module to be tested
• module8 my_module (reset, clock, ld, din,
  ack_i, dout, stb)

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Waveforms