Title: MIPS
1MIPS ????? ????? ?? ????
???????? ???????? ?????? ??? ???? ?????? R-type
?- I-type ??? ????? ??????? add, sub, or, xor,
and, slt, lw, sw, beq, j ????? ?????? ???? ????
??????? ?????? ?????? ??? ???? bne, addi, jal,
jr
2??? ????? ??????
3???? ????? ????? ?????
- (1) FETCH ??? ????? ???????? ?"? ?????? ?????
?-PC. - (2) DECODE ???? ?? ?????? ???? ?? ???????
??????? (??? ?? ?????). - (3) EXECUTE ????? ?-ALU ??? ?? ??????, ?? ?????
?????. - (4) MEMORY ????? ?????? ???? ????? ????? ??
????? ??????? (Store) ?? ????? ???????? (Load). - (5) WRITE BACK ??? ????? ????? ????? ?????.
4 ???? ?? ????? ????? ?????? ???? ????? ??????
???? ????? - ??????? ?? ?? ?????, ?? ????? ????
???? ???????? ?? ???? ????? (?? ????)
5 Single cycle data paths
Processor uses synchronous logic design (a
clock).
6Edge-Triggered D Flip Flops
Value of D is sampled on positive clock edge.
Q outputs sampled value for rest of cycle.
D
Q
7 Single cycle data paths Definition
All instructions execute in a single cycle of the
clock (positive edge to positive edge)
Advantage a great way to learn CPUs.
Drawbacks unrealistic hardware assumptions, slow
clock period
8Recall MIPS R-format instructions
Syntax ADD 8 9 10
Semantics 8 9 10
Fetch next inst from memory012A4020
Retrieve register values 9 10
Add 9 to 10
Place this sum in 8
Prepare to fetch instruction that follows the ADD
in the program.
9 Separate Read-Only Instruction Memory
Reads are combinational Put a stable address on
input, a short time later data appears on output.
????? (?????) ???? ??????? ???????? (Instruction
Memory Data Memory)
????? ??????? ?????? ?? ??????? ????
10??? 1 Straight-line Instruction Fetch
Fetching straight-line MIPS instructions requires
a machine that generates this timing diagram
Why do we increment every clock cycle?
Why 4 and not 1?
11 New Component Register (for PC)
PC
32
32
Din
Dout
Clk
In later examples, we will add an enable input
clock edge updates state only if enable is high
12 New Component A 32-bit adder (ALU)
13 Design Straight-line Instruction Fetch
State machine design in the service of an ISA
Instr Mem
32
PC
32
32
32
Addr
Data
D
Q
32
32
0x4
4 in hexadecimal
Clk
14Goal 1 An R-format single-cycle CPU
Syntax ADD 8 9 10
Semantics 8 9 10
Fetch next inst from memory012A4020
Retrieve register values 9 10
Add 9 to 10
Place this sum in 8
Prepare to fetch instruction that follows the ADD
in the program.
15Register files
Why is R0 special?
En
Q
R1
D
En
Q
R2
D
...
En
R31
Q
D
32
16 Register File Schematic Symbol
Why do we need WE (Write Enable)?
If we had a register file w/o WE, how could we
work around it?
17Goal 1 An R-format single-cycle CPU
Syntax ADD 8 9 10
Semantics 8 9 10
Fetch next inst from memory012A4020
Retrieve register values 9 10
Add 9 to 10
Place this sum in 8
Prepare to fetch instruction that follows the ADD
in the program.
18 Computing engine of the R-format CPU
Decode fields to get ADD 8 9 10
Logic
What do we do with WE?
19 Putting it all together ...
To rs1, rs2, ws, op decode logic ...
Logic
Is it safe to use same clock for PC and RegFile?
20 Reminder How data flows after posedge
PC
D
Q
21 Next posedge Update state and repeat
PC
D
Q
22A CPU capable of R-type instructions only
??? ?? ???? ?????
4
Adder
6
3126
Instruction Memory
PC
6
50funct
23????? ?????????. ????? ?? ????? ????
?-decode(????? ?-write back)
Read
register
1
Read
data
1
Read
2
????? ???????
register
Registers
Write
Read
register
data
2
Write
Data
Data
24Arithmetic Logic operation
ALU operation
Read
ALU operation
register
1
Read
data
1
Zero
Read
register
2
Instruction
Registers
ALU
Write
ALU
register
Read
result
data
2
ALU
Write
Data
?????? ??????? ?????? ??? ????? R-type
25A CPU capable of R-type instructions only
??? ?? ???? ?????
4
Adder
6
3126
Reg File
Instruction Memory
PC
ALU
6
50funct
26A CPU capable of R-type instructions only
??? ?? ???? ?????
4
Adder
6
3126
Reg File
Instruction Memory
PC
ALU
6
50funct
27The internal structure of the Register File
Rd reg 1 ( Rs)
32
5
32
32
32
32
Read data 1
write data
32
32
32
Rd reg 2 ( Rt)
5
32
32
32
Read data 2
32
32
Wr reg ( Rd)
5
E
RegWrite
?????? ???? ??????? ??????? ????? ?? ??? ????????
????? ?????? ???? ????????? ?????? (?????? ?????
????)
28A CPU capable of R-type instructions only
4
Adder
6
3126
RegWrite
Reg File
Instruction Memory
PC
ALU
29A CPU capable of R-type instructions only
Instruction Memory
Reg File
PC
ALU
30A CPU capable of R-type instructions only
4
Instruction Memory
Reg File
ALU
PC
31A CPU capable of R-type instructions only
4
Adder
6
3126
RegWrite
6
50funct
ALU control
Reg File
Instruction Memory
PC
ALU
32??? ?? 2 I-format ALU instructions
Syntax ORI 8 9 64
Semantics 8 9 64
Zero-extend 0x8000 ? 0x00008000
Sign-extend 0x8000 ? 0xFFFF8000
Some MIPS instructions zero-extend immediate
field, other instructions sign-extend.
33 Computing engine of the I-format CPU
Decode fields to get ORI 8 9 64
32
32
In a Verilog implementation, what should we do
with rs2?
34Merging data paths ...
two read ports
R-format
How many ?
I-format
Where ?
35 The merged data path ...
ALUctr
36Load,Store ????? ??????
Write
Read
address
Read
data
Write
address
Data
Write
memory
data
Read
??? ???? ?????? ?- data ???? ???? ????? ????? ???
?? ?? ???? sign extension ?? ?- imm ???? ?? 16bit
37 Loads, Stores, and Data Memory ...
Syntax LW 1, 32(2)
Syntax SW 3, 12(4)
Action 1 M2 32
Action M4 12 3
Zero-extend or sign-extend immediate field?
Writes are clocked If WE is high, memory Addr
captures Din on positive edge of clock.
Note Not a realistic main memory (DRAM) model ...
38???? ?- CPU?
Instruction Memory
CPU
PC
Data Memory
39A CPU capable of lw instructions only
4
Adder
6
3126
add
RegWrite1
Reg File
Data Memory
Instruction Memory
PC
ALU
Address
D. Out
5
16
150
Sext 16-gt32
40A CPU capable of lw instructions only
4
Adder
6
3126
add
RegWrite1
Reg File
Data Memory
Instruction Memory
PC
ALU
Address
D. Out
5
16
150
Sext 16-gt32
41A CPU capable of lw sw instructions only
4
MeWrite1
Adder
6
3126
add
RegWrite0
Reg File
Data Memory
Instruction Memory
PC
ALU
Address
5
D.In
16
150
Sext 16-gt32
42A CPU capable of R-type lw instructions
(principle)
4
Adder
6
3126
add
RegWrite
6
50funct
ALU control
Reg File
Data Memory
Instruction Memory
PC
ALU
Address
5
16
150
Sext 16-gt32
43A CPU capable of R-type lw instructions
4
Adder
6
3126
add
RegWrite
6
50funct
ALU control
Reg File
Data Memory
Instruction Memory
PC
ALU
Address
D. Out
5
Rd
16
150
Sext 16-gt32
44A CPU capable of R-type lw/sw instructions
4
MemWrite
Adder
6
3126
add
RegWrite
6
50funct
ALU control
Reg File
Data Memory
Instruction Memory
PC
ALU
Address
D. Out
5
Rd
D.In
16
150
Sext 16-gt32
45 Conditional Branches in MIPS ...
Syntax BEQ 1, 2, 12
Action If (1 ! 2), PC PC 4
Action If (1 2), PC PC 4 48
Why is this encoding a good idea?
Zero-extend or sign-extend immediate field?
46Branch ??????? ?????? ??????
PC4 ???? ?- Fetch
Adder
In addresses, we always shift left by two bits
Sum
Shift
Branch
Read
left
2
Target
register
1
Read
Read
data
1
register
2
Registers
Write
Instruction
Zero
register
?????
ALU
Read
Write
data
2
??????
Data
?????
??????
16
32
Sigh
??????
Extend
??
???????
47 Design Instruction Fetch with Branch
Syntax BEQ 1, 2, 12
Action If (1 ! 2), PC PC 4
Action If (1 2), PC PC 4 48
Instr Mem
PC
32
32
Addr
Data
D
Q
32
Clk
48????? ?? ???????
M
u
x
Add
4
ADD
Write
PC
Read
Zero
data
1
Instruction
Read
ALU
data
2
Data
memory
Read
16
32
49What is single cycle control?
ALUctr
Equal
Ext
RegDest
ALUsrc
ExtOp
RegWr
50???? ????
P
C
S
r
c
M
u
Add
A
d
d
x
ALU result
4
Shift left 2
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51Control
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52Control
53ALU control
ALU control output000 AND001 OR010 add110 s
ubtract111 set-on-less-than (sign of rs-rt
-gt rd)
00 lw, sw01 beq, 10 arithmetic
ALUop
54????? ?- jump
????? ?????? J 101101111011
?????? ???? ????? ?????? 1111110111001
4 bits 26 bits 2 bits
????? ????? ??????
101 101111011
????? ????? ?????
00
101 101111011
0110
101 101111011
????? 4 ????? ???????
00
101 101111011
0110
?????? ??????
55Jump
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