Combinational Logic

1
Chapter 4
2
Combinational Circuits

• Output is function of input only
• i.e. no feedback
• When input changes output may change (after a
  delay)

Combinational Circuits
n inputs
m outputs



3
Combinational Circuits

• Analysis
• Given a circuit find out its function
• Function may be expressed as
• Boolean function
• Truth table
• Design
• Given a desired function determine its circuit
• Function may be expressed as
• Boolean function
• Truth table

4
Analysis Procedure

• Boolean Expression Approach

ABC
ABC
ABCABCABC
(AB)(AC)(BC)
ABACBC
F1ABCABCABCABC F2ABACBC
5
Analysis Procedure

• Truth Table Approach

0 0
0 0 0 0 0 0 0 0 0 0
0 0
0 0 0 0 0
0
0
1
0
6
Analysis Procedure

• Truth Table Approach

0 0 1 0 0 1 0 0 0 1
0 1
0 1 0 0 0
1
1 0
1
1
0
7
Analysis Procedure

• Truth Table Approach

0 1 0 0 1 0 0 1 0 0
1 0
0 1 0 0 0
1
1 0
1
1
0
8
Analysis Procedure

• Truth Table Approach

0 1 1 0 1 1 0 1 0 1
1 1
0 1 0 0 1
0
0
0 1
0
1
9
Analysis Procedure

• Truth Table Approach

1 0 0 1 0 0 1 0 1 0
0 0
0 1 0 0 0
1
1
1 0
1
0
10
Analysis Procedure

• Truth Table Approach

1 0 1 1 0 1 1 0 1 1
0 1
0 1 0 1 0
0
0
0
0 1
1
11
Analysis Procedure

• Truth Table Approach

1 1 0 1 1 0 1 1 1 0
1 0
0 1 1 0 0
0
0
0
0 1
1
12
Analysis Procedure

• Truth Table Approach

1 1 1 1 1 1 1 1 1 1
1 1
1 1 1 1 1
1
0
0
1
1 1
F1ABCABCABCABC
F2ABACBC
13
Design Procedure

• Given a problem statement
• Determine the number of inputs and outputs
• Derive the truth table
• Simplify the Boolean expression for each output
• Produce the required circuit
• Example
• Design a circuit to convert a BCD code to
  Excess 3 code

• 4-bits
• 0-9 values

• 4-bits
• Value3

14
Design Procedure

• BCD-to-Excess 3 Converter

w ABCBD
x BCBDBCD
y CDCD
z D
15
Design Procedure

• BCD-to-Excess 3 Converter

w A B(CD)
y (CD) CD
x B(CD) B(CD)
z D
16
Seven-Segment Decoder
BCD code
a w y xz xz
b . . .
c . . .
d . . .
17
Binary Adder

• Half Adder
• Adds 1-bit plus 1-bit
• Produces Sum and Carry

x y --- C S
18
Binary Adder

• Full Adder
• Adds 1-bit plus 1-bit plus 1-bit
• Produces Sum and Carry

x y z --- C S
S xyzxyzxyzxyz x y z
C xy xz yz
19
Binary Adder

• Full Adder

S xyzxyzxyzxyz x y z
C xy xz yz
x y z
S C
S C
x y z
20
Binary Adder

• Full Adder

HA
HA
x y z
S C
x y z
S C
21
Binary Adder
c3 c2 c1 . x3 x2 x1 x0 y3 y2 y1
y0
-------- Cy S3 S2 S1 S0
Carry Propagate Addition
x3 x2 x1
x0
y3 y2 y1
y0
0
FA
FA
FA
FA
C4 C3 C2
C1
S3 S2 S1
S0
22
Binary Adder

• Carry Propagate Adder

x3 x2 x1 x0
x7 x6 x5 x4
y3 y2 y1 y0
y7 y6 y5 y4
CPA
A3 A2 A1 A0
B3 B2 B1 B0
0
C0
Cy
S3 S2 S1 S0
S3 S2 S1 S0
S7 S6 S5 S4
23
BCD Adder

• 4-bits plus 4-bits
• Operands and Result 0 to 9

x3 x2 x1 x0 y3 y2 y1 y0 -------- Cy
S3 S2 S1 S0
Invalid Code
Wrong BCD Value
0001 1000
24
BCD Adder

6
25
BCD Adder

• Correct Binary Adders Output (6)
• If the result is between A and F
• If Cy 1

Err S3 S2 S3 S1
26
BCD Adder
Err
27
Binary Subtractor

• Use 2s complement with binary adder
• x y x (-y) x y 1

28
Binary Adder/Subtractor

• M Control Signal (Mode)
• M0 F x y
• M1 F x y

29
Overflow

• Unsigned Binary Numbers
• 2s Complement Numbers

Carry
Overflow
30
Magnitude Comparator

• Compare 4-bit number to 4-bit number
• 3 Outputs
• Expandable to more number of bits

A3A2A1A0 B3B2B1B0
Magnitude Comparator
AB
31
Magnitude Comparator
32
Magnitude Comparator
x3 x2 x1 x0
x7 x6 x5 x4
y3 y2 y1 y0
y7 y6 y5 y4
MagnitudeComparator
A3 A2 A1 A0
B3 B2 B1 B0
0 1 0
I(AB) I(AB) I(AAB
AB
33
Decoders

• Extract Information from the code
• Binary Decoder
• Example 2-bit Binary Number

Only one lamp will turn on
1 0 0 0
0 0
34
Decoders

• 2-to-4 Line Decoder

35
Decoders

• 3-to-8 Line Decoder

36
Decoders

• Enable Control

37
Decoders

• Expansion

I2 I1 I0
38
Decoders

• Active-High / Active-Low

39
Implementation Using Decoders

• Each output is a minterm
• All minterms are produced
• Sum the required minterms
• Example Full Adder
• S(x y z) (1 2 4 7)
• C(x y z) (3 5 6 7)

40
Implementation Using Decoders
41
Encoders

• Put Information into code
• Binary Encoder
• Example 4-to-2 Binary Encoder

Only one switch should be activated at a time
42
Encoders

• Octal-to-Binary Encoder (8-to-3)

43
Priority Encoders

• 4-Input Priority Encoder

44
Encoder / Decoder Pairs
BinaryEncoder
BinaryDecoder
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
I7 I6 I5 I4 I3 I2 I1 I0
Y2 Y1 Y0
I2 I1 I0
45
Multiplexers
46
Multiplexers

• 2-to-1 MUX
• 4-to-1 MUX

47
Multiplexers

• Quad 2-to-1 MUX

x3 x2 x1 x0
y3 y2 y1 y0
S
48
Multiplexers

• Quad 2-to-1 MUX

Extra Buffers
49
Implementation Using Multiplexers

• ExampleF(x y) (0 1 3)

1 1 0 1
F
x y
50
Implementation Using Multiplexers

• ExampleF(x y z) (1 2 6 7)

0 1 1 0 0 0 1 1
F
x y z
51
Implementation Using Multiplexers

• ExampleF(x y z) (1 2 6 7)

z
F z
F
z
0
F z
1
F 0
x y
F 1
52
Implementation Using Multiplexers

• ExampleF(A B C D) (1 3 4 11 12 13
  14 15)

D
F D
D
F D
D
0
F D
F
0
F 0
D
F 0
1
F D
1
F 1
F 1
A B C
53
Multiplexer Expansion

• 8-to-1 MUX using Dual 4-to-1 MUX

0 0
1
54
DeMultiplexers
55
Multiplexer / DeMultiplexer Pairs
MUX
DeMUX
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
I7 I6 I5 I4 I3 I2 I1 I0
Y
I
S2 S1 S0
S2 S1 S0
Synchronize
x2 x1 x0
y2 y1 y0
56
DeMultiplexers / Decoders
57
Three-State Gates

• Tri-State Buffer
• Tri-State Inverter

A
Y
C
58
Three-State Gates
A
Y
C
B
Not Allowed
D
A if C 1 B if C 0
Y
59
Three-State Gates
I3
I2
Y
I1
I0
BinaryDecoder
Y3 Y2 Y1 Y0
I1 I0 E
S1
S0
E
60
Homework

• Mano
• Chapter 4
• 4-2
• 4-3
• 4-5
• 4-11
• 4-13
• 4-27
• 4-28
• 4-31
• 4-32
• 4-33
• 4-35

61
Homework

• Mano

62
Homework
63
Homework
64
Homework
65
Homework
66
Homework