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PPT – Combinational Logic PowerPoint presentation | free to view - id: 71b3-NzI2N

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Chapter 4

Combinational Circuits

- Output is function of input only
- i.e. no feedback
- When input changes, output may change (after a

delay)

Combinational Circuits

n inputs

m outputs

?

Combinational Circuits

- Analysis
- Given a circuit, find out its function
- Function may be expressed as
- Boolean function
- Truth table
- Design
- Given a desired function, determine its circuit
- Function may be expressed as
- Boolean function
- Truth table

Analysis Procedure

- Boolean Expression Approach

ABC

ABC

AB'C'A'BC'A'B'C

(AB)(AC)(BC)

ABACBC

F1AB'C'A'BC'A'B'CABC F2ABACBC

Analysis Procedure

- Truth Table Approach

0 0

0 0 0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0

0

1

0

Analysis Procedure

- Truth Table Approach

0 0 1 0 0 1 0 0 0 1

0 1

0 1 0 0 0

1

1 0

1

1

0

Analysis Procedure

- Truth Table Approach

0 1 0 0 1 0 0 1 0 0

1 0

0 1 0 0 0

1

1 0

1

1

0

Analysis Procedure

- Truth Table Approach

0 1 1 0 1 1 0 1 0 1

1 1

0 1 0 0 1

0

0

0 1

0

1

Analysis Procedure

- Truth Table Approach

1 0 0 1 0 0 1 0 1 0

0 0

0 1 0 0 0

1

1

1 0

1

0

Analysis Procedure

- Truth Table Approach

1 0 1 1 0 1 1 0 1 1

0 1

0 1 0 1 0

0

0

0

0 1

1

Analysis Procedure

- Truth Table Approach

1 1 0 1 1 0 1 1 1 0

1 0

0 1 1 0 0

0

0

0

0 1

1

Analysis Procedure

- Truth Table Approach

1 1 1 1 1 1 1 1 1 1

1 1

1 1 1 1 1

1

0

0

1

1 1

F1AB'C'A'BC'A'B'CABC

F2ABACBC

Design Procedure

- Given a problem statement
- Determine the number of inputs and outputs
- Derive the truth table
- Simplify the Boolean expression for each output
- Produce the required circuit
- Example
- Design a circuit to convert a BCD code to

Excess 3 code

- 4-bits
- 0-9 values

- 4-bits
- Value3

Design Procedure

- BCD-to-Excess 3 Converter

w ABCBD

x BCBDBCD

y CDCD

z D

Design Procedure

- BCD-to-Excess 3 Converter

w A B(CD)

y (CD) CD

x B(CD) B(CD)

z D

Seven-Segment Decoder

BCD code

a w y xz xz

b . . .

c . . .

d . . .

Binary Adder

- Half Adder
- Adds 1-bit plus 1-bit
- Produces Sum and Carry

x y --- C S

Binary Adder

- Full Adder
- Adds 1-bit plus 1-bit plus 1-bit
- Produces Sum and Carry

x y z --- C S

S xy'z'x'yz'x'y'zxyz x ? y ? z

C xy xz yz

Binary Adder

- Full Adder

S xy'z'x'yz'x'y'zxyz x ? y ? z

C xy xz yz

x y z

S C

S C

x y z

Binary Adder

- Full Adder

HA

HA

x y z

S C

x y z

S C

Binary Adder

c3 c2 c1 . x3 x2 x1 x0 y3 y2 y1

y0

-------- Cy S3 S2 S1 S0

Carry Propagate Addition

x3 x2 x1

x0

y3 y2 y1

y0

0

FA

FA

FA

FA

C4 C3 C2

C1

S3 S2 S1

S0

Binary Adder

- Carry Propagate Adder

x3 x2 x1 x0

x7 x6 x5 x4

y3 y2 y1 y0

y7 y6 y5 y4

CPA

A3 A2 A1 A0

B3 B2 B1 B0

0

C0

Cy

S3 S2 S1 S0

S3 S2 S1 S0

S7 S6 S5 S4

BCD Adder

- 4-bits plus 4-bits
- Operands and Result 0 to 9

x3 x2 x1 x0 y3 y2 y1 y0 -------- Cy

S3 S2 S1 S0

Invalid Code

Wrong BCD Value

0001 1000

BCD Adder

? ? ? ? ? ? ? ? ?

6

BCD Adder

- Correct Binary Adders Output (6)
- If the result is between A and F
- If Cy 1

Err S3 S2 S3 S1

BCD Adder

Err

Binary Subtractor

- Use 2s complement with binary adder
- x y x (-y) x y 1

Binary Adder/Subtractor

- M Control Signal (Mode)
- M0 ? F x y
- M1 ? F x y

Overflow

- Unsigned Binary Numbers
- 2s Complement Numbers

Carry

Overflow

Magnitude Comparator

- Compare 4-bit number to 4-bit number
- 3 Outputs
- Expandable to more number of bits

A3A2A1A0 B3B2B1B0

Magnitude Comparator

AB

Magnitude Comparator

Magnitude Comparator

x3 x2 x1 x0

x7 x6 x5 x4

y3 y2 y1 y0

y7 y6 y5 y4

MagnitudeComparator

A3 A2 A1 A0

B3 B2 B1 B0

0 1 0

I(AB) I(AB) I(AAB

AB

Decoders

- Extract Information from the code
- Binary Decoder
- Example 2-bit Binary Number

Only one lamp will turn on

1 0 0 0

0 0

Decoders

- 2-to-4 Line Decoder

Decoders

- 3-to-8 Line Decoder

Decoders

- Enable Control

Decoders

- Expansion

I2 I1 I0

Decoders

- Active-High / Active-Low

Implementation Using Decoders

- Each output is a minterm
- All minterms are produced
- Sum the required minterms
- Example Full Adder
- S(x, y, z) ?(1, 2, 4, 7)
- C(x, y, z) ?(3, 5, 6, 7)

Implementation Using Decoders

Encoders

- Put Information into code
- Binary Encoder
- Example 4-to-2 Binary Encoder

Only one switch should be activated at a time

Encoders

- Octal-to-Binary Encoder (8-to-3)

Priority Encoders

- 4-Input Priority Encoder

Encoder / Decoder Pairs

BinaryEncoder

BinaryDecoder

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

I7 I6 I5 I4 I3 I2 I1 I0

Y2 Y1 Y0

I2 I1 I0

Multiplexers

Multiplexers

- 2-to-1 MUX
- 4-to-1 MUX

Multiplexers

- Quad 2-to-1 MUX

x3 x2 x1 x0

y3 y2 y1 y0

S

Multiplexers

- Quad 2-to-1 MUX

Extra Buffers

Implementation Using Multiplexers

- ExampleF(x, y) ?(0, 1, 3)

1 1 0 1

F

x y

Implementation Using Multiplexers

- ExampleF(x, y, z) ?(1, 2, 6, 7)

0 1 1 0 0 0 1 1

F

x y z

Implementation Using Multiplexers

- ExampleF(x, y, z) ?(1, 2, 6, 7)

z

F z

F

z

0

F z

1

F 0

x y

F 1

Implementation Using Multiplexers

- ExampleF(A, B, C, D) ?(1, 3, 4, 11, 12, 13,

14, 15)

D

F D

D

F D

D

0

F D

F

0

F 0

D

F 0

1

F D

1

F 1

F 1

A B C

Multiplexer Expansion

- 8-to-1 MUX using Dual 4-to-1 MUX

0 0

1

DeMultiplexers

Multiplexer / DeMultiplexer Pairs

MUX

DeMUX

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

I7 I6 I5 I4 I3 I2 I1 I0

Y

I

S2 S1 S0

S2 S1 S0

Synchronize

x2 x1 x0

y2 y1 y0

DeMultiplexers / Decoders

Three-State Gates

- Tri-State Buffer
- Tri-State Inverter

A

Y

C

Three-State Gates

A

Y

C

B

Not Allowed

D

A if C 1 B if C 0

Y

Three-State Gates

I3

I2

Y

I1

I0

BinaryDecoder

Y3 Y2 Y1 Y0

I1 I0 E

S1

S0

E

Homework

- Mano
- Chapter 4
- 4-2
- 4-3
- 4-5
- 4-11
- 4-13
- 4-27
- 4-28
- 4-31
- 4-32
- 4-33
- 4-35

Homework

- Mano

Homework

Homework

Homework

Homework

Homework

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