A Living Roadmap for Semiconductors October 4, 2000 SRC Review

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A Living Roadmap for SemiconductorsOctober 4,
2000 SRC Review

• Andrew B. Kahng
• UCSD CSE and ECE Departments
• abk_at_ucsd.edu
• effective January 1, 2001

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Outline

• The Design Technology Gap and the GSRC C.A.D.
  Theme
• On Roadmaps
• The GSRC Technology Extrapolation (GTX) System
  Toward a Living Roadmap
• A Living Roadmap for Semiconductors (and Design)

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Motivation The Design Technology Gap

• Design Productivity Gap
• Well-documented, threatens quality and value of
  designs
• huge cost to semiconductor industry
• Most research change the Design Problem, invent
  new algorithms...
• Premise of MARCO GSRC Calibrating Achievable
  Design Theme Design Productivity
  Gap Design Technology Productivity Gap
• Problem Must improve Time-To-Market and
  Quality-of-Result for Design Technology
• Goal improve CAD Industry Productivity by
  changing how we specify, develop, and measure and
  improve Design Technology

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Facets of the Design Technology Gap

• Facets
• No clear industry-wide RD agenda
• Time-to-Market 5-7 years to get a leading-edge
  algorithm into production EDA
• designers battle todays design problems with
  yesterdays design technology
• QOR difficult to evaluate impact of new tools
  on overall design process
• QOR published descriptions insufficient for
  replication or even comparison of algorithms
• CAD RD cannot identify, evaluate or reuse the
  CAD technology leading edge research and
  innovation stall
• Causes
• Lack of clear roadmapping for Design Technology
  w.r.t. ITRS, application markets
• Lack of Foundation CAD-IP interoperable,
  reusable, commodity infrastructure
• Lack of resources, and relative over-resourcing
  of non-strategic, de facto commodity technology
• Lack of standard metrics, benchmarks for Design
  Technology
• More maturity needed w.r.t. control,
  strategic-vs-commodity distinction, etc.

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Goal Improved Design Technology Productivity

• The GSRC C.A.D. Theme promotes mature,
  coopetitive cultures and shared, open
  infrastructures that lead to improved creation of
  design technology
• Improved vision and design technology planning
  (specify)
• What will the design problem look like? What do
  we need to solve?
• Improved execution (develop)
• How can we quickly develop the right design
  technology (TTM)?
• Improved measurement (measure and improve)
• Did we solve the problem (QOR)? Did the design
  process improve? Did we
  increase the envelope of achievable design?

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A Vision of the Future

• Improved vision and design technology planning
  (specify)
• What will the design problem look like? What do
  we need to solve?
• Accurate roadmapping for Design (and Process)
  Technology (Living Roadmap)
• 1.5x more focused RD resources
• Improved execution (develop)
• How can we quickly develop the right design
  technology (TTM)?
• Reusable, commodity, Foundation CAD-IP (
  academic publication standards)
• reduce TTM to 2-3 yrs, 2x better leveraged
  RD and academic resources, 2x
  increase in searched solution space
  (mix-and-match flow optimizations)
• Improved measurement (measure and improve)
• Did we solve the problem (QOR)? Did the design
  process improve? Did we
  increase the envelope of achievable design?
• Design tool/process metrics, design process
  instrumentation and CPI
• 1.5x increase in searched solution space
  (flow and process optimizations)
• Design Technology Productivity improves Design
  Productivity

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Outline

• The Design Technology Gap and the GSRC C.A.D.
  Theme
• On Roadmaps
• The GSRC Technology Extrapolation (GTX) System
  Toward a Living Roadmap
• A Living Roadmap for Semiconductors (and Design)

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What is Roadmapping? (Ideally...)

• Roadmapping drives development of (e.g., CAD)
  technology
• System architects, designers, CAD managers use
  roadmaps to determine
• tough problems
• risks,
• EDA suppliers use roadmaps to determine
• RD investment
• product pipeline
• Government and consortia use roadmaps to
  determine levels of investment
• Roadmaps serve as a guide to the most promising
  directions, the most critical problems

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What is a Roadmap? (In reality...)

• Self-fulfilling prophecy ?
• Moores Law (Circuits per chip)
  2(year-1975)/1.5 (Gordon Moore, 1975 IEDM)
• More than anything, once something like this
  gets established, it becomes more or less a
  self-fulfilling prophecy. The Semiconductor
  Industry Association puts out a technology road
  map, which continues this generation turnover
  every three years. Everyone in the industry
  recognizes that if you don't stay on essentially
  that curve they will fall behind. So it sort of
  drives itself. (Gordon Moore, 1996)
• Always wrong, yet comprised of meta-laws ?
• Reasons for Moores Law (1975) die size growth,
  feature size decrease, circuit/device cleverness
• Gordon Moore, 1975 "There is no room left to
  squeeze anything out by being clever. Going
  forward from here we have to depend on the two
  size factors - bigger dice and finer dimensions.
  (Gordon Moore, 1995)
• Geopoliticoeconomic ?
• QUIZ Rank the following four regions by
  decreasing order of aggressiveness in feature
  size United States, Japan, Europe,
  East Asia

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What is a Roadmap? (In reality...)

• Sensitive
• Example 1 Cell Area Factor for memory
• Scenario 1 8x/1999 2.5x/2014
• Scenario 2 8x/1999 4x/2016
• Example 2 Litho Field Size Maximum Limit
• Scenario 1 4x magnification, 6-inch reticle
  (800mm2 intro, 400 mm2 production)
• Scenario 2 5x magnification, 6-inch reticle
  (572mm2 intro, 286 mm2 production)
• Example 3 L2 Cache Size for High-Perf MPU
  (baseline of ramp going forward)
• Scenario 1 2MB on-chip 6t SRAM 170mm2 core
  280mm2 SRAM 450mm2 in 1999
• Scenario 2 1MB on-chip 6t SRAM 170mm2 core
  140mm2 SRAM 310mm2 in 1999
• QUIZ By what factor will the high-performance
  MPU transistor count at the end of the Roadmap
  change if we switch between Scenario 1 and
  Scenario 2 ?

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What is a Roadmap? (In reality...)

• Always evolving
• In gate length in resist vs. physical, CMP
  dishing, SOC complexity, ...
• Out NRE cost of logic (including design cost!),
  ...
• In flux in volume production, no known
  solution, high-perf MPU, ...
• Conflicted between Forecasts vs. Statements of
  Needs
• a statement of technology needs in various
  areas, driven by a forecast of lithography
  capability (D. Jensen, AMD)
• a hybrid of the most realistic aggressive
  targets, balanced by the tension created by the
  red limits of unknown solutions (A. Allan,
  Intel)
• Paralyzed by dependencies
• who owns package pins/balls? Test?
  Assembly/Packaging? Design?
• how does one go about changing a number, checking
  for interactions ?
• Law of Roadmaps If its worth roadmapping, it
  cant be roadmapped.

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ITRS Acceleration
500
1994
350
250
1997
Technology Node
180
1998/1999
130
90
DRAM Half Pitch
100
Minimum Feature
65
70
MPU/ASIC Gate Physical
45
50
Scenarios
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MPU/ASIC Gate In Resist
35
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1.0 1.5 2.0
25
16
Year of Production
.7x per technology node (.5x per 2 nodes)
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What Should a Roadmap Be? (More Practically...)

• Comprehensive and best possible
• Robust
• Flexible and adaptive
• A Living Roadmap ???

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Outline

• The Design Technology Gap and the GSRC C.A.D.
  Theme
• On Roadmaps
• The GSRC Technology Extrapolation (GTX) System
  Toward a Living Roadmap
• A Living Roadmap for Semiconductors (and Design)

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Technology Extrapolation
What is the most power-efficient noise management
strategy?

• Evaluates impact of
• design technology
• process technology
• Evaluates impact on
• achievable design
• associated design problems
• What do we need to solve?
• What will the design problem look like ?
• Roadmapping to drive Design Technology

How and when do L, SOI, SER, etc. matter?
Will layout tools need to perform process
simulation to effectively model cross-die and
cross-wafer manufacturing variation?
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Optimal Repeater Sizing

• Most commonly used optimal repeater sizing
  expression (Bakoglu)
• New study
• Sweep repeater size for single stage in the chain
  
• Examine both delay and energy-delay product

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Cu Resistivity Effect of Line Width Scaling
ITRS 1999 Line width (nm)
280 170 133
Global Semiglobal Local
525 320 250
95 58 48
Effect of 5 nm Barrier
Effect of Electron Scattering

• Conformal 5 nm barrier assumed
• Even a 5 nm barrier will increase resistivity
  drastically

• No barrier assumed
• Electron scattering increases resistivity
• Lowering temperature has a big effect

source MARCO IFRC
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Technology Extrapolation Today

• Many Roadmaps
• ITRS, JISSO, STARC, Roadmaps
• University tools SUSPENS, GENESYS, RIPE, BACPAC,
  
• Industry tools HIVE/AIM, ...
• Observations
• everyone predicts same parameters but different
  assumptions, inputs near-total duplication of
  effort !!!
• no documentation or visibility into internal
  calculations
• hard-wired ? cannot easily test other modeling
  choices
• missing models of CAD tools and optimizations
  (what is really achievable?)
• missing scope, comprehensive coverage

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A Shared Technology Extrapolation System

• Flexibility
• edit or define new parameters and relations
  between them
• perform specific studies (but different studies
  at different times)
• Quality
• continuous improvements
• world-wide participation of experts
• Transparency
• open-source mechanism
• models visible to the user
• No more redundant effort
• permanent repository of first choice
• adoptability and maintainability

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GTX GSRC Technology Extrapolation System

• GTX framework for shared technology
  extrapolation
• Living Roadmap Repository, sanity-checker
  for 2001 ITRS renewal (via US Design TWG,
  (inter-) ITWG activity)
• Open-source http//vlsicad.cs.ucla.edu/GSRC/GTX
  /

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Knowledge Representation

• Human-readable ASCII grammar

rule BACPAC_dl_chip description output double
m dl_chip inputs double m2 dA_chip body
sqrt(dA_chip) reference endrule
parameter dl_chip type double units
m default 1e-2 description chip side
length reference endparameter
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Knowledge Representation

• Human-readable ASCII grammar
• Benefits
• Easy creation/sharing of parameters/rules by
  multiple users
• D. Sylvester and Y. Cao device and power, SOI
  modules that drop in to GTX
• P.K. Nag Yield modeling
• Extensible to models of arbitrary complexity
  (specialized prediction methods, technology data
  sets, optimization engines)
• Avant! Apollo or Cadence SE PR tool just
  another wirelength estimator
• Applies to any domain of work in semiconductors,
  VLSI CAD
• Transistor sizing, single wire optimizations,
  system-level wiring predictions,

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Parameters

• Description of technology, circuit and design
  attributes
• Importance of consistent naming cannot be
  overstated
• Naming conventions for parameters
• ltprepositiongt _ ltprincipalgt _ qualifier _
  ltplacegt _ ltqualifiergt _ ltadverbialgt _
  ltindexgt _ ltunitgt
• Example r_int_tot_lyr_pu_dl
• Requirements
• Relatively easy to understand parameter from its
  name
• Distinguishable (no two parameters should have
  the same name)
• r_int (interconnect resistance) r_int
  (interconnect resistivity) ?
• Unique (no two names for the same parameter)
• R_int R_wire ?
• Sortable (important literals come first)
• Software to automatically check parameter naming

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Rules

• Methods to derive unknown from known parameters
• ASCII rules
• Laws of physics, models of electrical behavior,
  statistical models
• Include closed-form expressions, vector
  operations, tables
• Storing of calibration data (e.g., technology
  files) for known process and design points in
  lookup tables
• Constraints, used to limit range during
  sweeping
• External executable rules
• Assume a callable executable (e.g., PERL script)
• Use command-line interface and transfer through
  files
• Allow complex semantics of a rule
• Code rules
• Implemented in C and linked into the inference
  engine

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Rule Chains

• Rule chains guide inference
• Acyclic set of rules
• Interactive specification and comparison of
  alternative modeling choices
• Studies
• Input values rules that make
• a rule chain
• User-controlled and savable
• Sweeping of a rule chain
• Evaluation of all combinations
• of multi-valued inputs
• Example clock frequency for
• different Rent exponents and
• varying logic depth

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GTX Engine

• Contains no domain-specific knowledge
• Evaluates rules in topological order
• Performs studies
• Multiple values through sweeping
• Runs on three platforms (Solaris, Windows and
  Linux)
• URL http//vlsicad.cs.ucla.edu/GSRC/GTX/

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Graphical User Interface (GUI)

• Provides user interaction
• Visualization (plotting, printing, saving to
  file)
• 4 views
• Parameters
• Rules
• Rule chain
• Values in chain

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Sensitivity Analysis of Cycle-time Models
Parameter Sensitivity

• Change parameter values and observe resulting
  difference in outputs

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Sensitivity Analysis of Cycle-time Models Model
Sensitivity

• Replace rule in a models rule chain by another
  models rule and observe the difference in outputs

BACPAC with rule from Fisher
BACPAC
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Delay Uncertainty Study

• Staggered repeaters
• Introduced in Kahng et al, VLSI Design 99 to
  reduce delay and noise

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Outline

• The Design Technology Gap and the GSRC C.A.D.
  Theme
• On Roadmapping
• The GSRC Technology Extrapolation (GTX) System
  Toward a Living Roadmap
• A Living Roadmap for Semiconductors (and Design)

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GTX Status

• Recent Developments
• GTX is multi-platform, open-source (MIT license)
• many industry downloads basis of development
  project at eSilicon (?)
• Third release of GTX September 3, 2000
• namespaces, partial rule chain evaluation, vector
  types, etc.
• Models/studies implemented
• cost/yield (CMU), SOI device/power
  (Synopsys/Berkeley), RLC interconnect modeling
  and optimization (SGI/UCLA/Synopsys/Berkeley/Sun),
  routability and layer assignment (UCLA/Ghent)
• GENESYS, RIPE source code translation into GTX
• Near-Term Futures
• Functionality annotations, intelligence,
  more direct Roadmap support
• Models/studies RLC interconnect noise/delay,
  manufacturing variability, clock distribution,
  DRAM/logic implementation tradeoffs, packaging
  tradeoffs, device layout density, ...
• GTX repository for ITRS-2001 ORTCs
  (transparent, living Roadmap)

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Roadmapping Challenges

• Valuation, evaluation of Design and Design
  Technology
• scope and definition of design technology, design
  processes ?
• formal metrics for QOR, effectiveness of design
  technology ?
• cost measures for design ? (e.g., as part of
  semiconductor NRE )
• Real linkage between Design, other TWGs in
  ITRS-2001 effort
• Test, Interconnect, Litho, PIDS, FEP,
  Assembly/Packaging, ...
• goal consistency and integrity of ITRS
• Contributions from across the semiconductor
  process and design communities
• best known methods and models best known data

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Toward Improved Design Technology Productivity

• The GSRC C.A.D. Theme promotes mature,
  coopetitive cultures and shared, open
  infrastructures that lead to improved creation of
  design technology (see http//vlsicad.cs.ucla.
  edu/GSRC/ )
• Improved vision and design technology planning
  (specify)
• What will the design problem look like? What do
  we need to solve?
• Answer Living Roadmap (The GSRC Technology
  Extrapolation (GTX) System)
• Improved execution (develop)
• How can we quickly develop the right design
  technology (TTM)?
• Answer CAD-IP Reuse (The GSRC Bookshelf for
  Fundamental CAD-IP)
• Improved measurement (measure and improve)
• Did we solve the problem (QOR)? Did the design
  process improve? Did we increase
  the envelope of achievable design?
• Answer Design Process Instrumentation,
  Optimization (METRICS)

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Make Your Contribution !!!

• U.S. Design Technical Working Group for ITRS-2001
  renewal
• structure, scope, content, links for Design,
  System Drivers chapters
• IEEE DATC Electronic Design Processes
  Subcommittee
• edps-all_at_eda.org EDP Workshop (April,
  Monterey CA)
• MARCO GSRC C.A.D. Theme
• Bookshelf for CAD-IP Reuse, METRICS Initiative
• http//vlsicad.cs.ucla.edu/GSRC/
• GTX
• new models and studies usability, use model
  feedback
• My contact info abk_at_ucsd.edu

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The Design Productivity Gap
Potential Design Complexity and Designer
Productivity
Equivalent Added Complexity
Logic Tr./Chip Tr./S.M.
68 /Yr compounded Complexity growth rate
21 /Yr compound Productivity growth rate

How many gates can I get for N?
3 Yr. Design
Year Technology Chip Complexity
Frequency Staff Staff Cost

• 250 nm 13 M
  Tr. 400 MHz 210
  90 M
• 250 nm 20 M
  Tr. 500 270
  120 M
• 180 nm 32 M
  Tr. 600 360
  160 M
• 2002 130 nm 130
  M Tr. 800 800
  360 M

Source SEMATECH
_at_ 150 k / Staff Yr. (In 1997 Dollars)
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Design Productivity Gap ? Low-Value Designs?
Percent of die area that must be occupied by
memory to maintain SOC design productivity
Source Japanese system-LSI industry
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Roadmap Process and Its Implications
(Ideally...)
Models and Discussion
Timing closure is a hard problem and will only
get harder
Implications to the Community
We will fund research on timing-aware
partitioning
Translation to Specific Research Agendas
Research Proposed to Implement Agenda
R. Newton, ICCAD99 panel
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Roadmap Process (More Practically...)
Models and Discussion
Timing closure is a hard problem and will only
get harder
Implications to the Community
Heres how my work is critical for addressing
your problem
Couched in Terms of Roadmap Implications
I can make a breakthrough in technology or
methodology
Research Proposed to Solve Hard Problem
R. Newton, ICCAD99 panel
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RLC Interconnect Delay Approximation

• Five different interconnect models
• Bakoglus model (RC)
• Alpert, Devgan and Kashyap, ISPD 2000 (RC)
• Ismail, Friedman and Neves, TCAD 19(1), 2000
  (RLC)
• Kahng and Muddu, TCAD 1997 (RLC)
• Extension of Alpert, Devgan and Kashyap, ISPD
  2000 (RLC)

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Cu Resistivity Barrier Deposition Technology
Atomic Layer Deposition (ALD) Ionized
PVD Collimated PVD

• 5 nm barrier assumed at the thinnest spot
• No scattering assumed, I.e., bulk resistivity

Interconnect dimensions scaled according to ITRS
1999
source MARCO IFRC