By: Roghoyeh Salmeh

1
RFIC DesignLow Noise Amplifier (LNA) Gain and
Noise Figure (NF) Optimization

• By Roghoyeh Salmeh

2
LNA gain and NF Optimization

• Introduction
• Review of gain and NF of a receiver
• LNAs design specification
• LNAs input stage small signal model
• Review of the published techniques
• Electrical models of ESD diodes and pads
• Quad Flat Non-leaded (QFN) package model
• Impact of the parasitic on the gain and NF of a
  common source cascode LNA
• Conclusions

3
Introduction

• The main objective in LNA design is to achieve
  simultaneous noise and input matching (SNIM) for
  a given power consumption.
• Researchers have paid a great deal of attention
  to the noise figure optimization of a common
  source cascode LNA.
• The objective of this presentation is to study
  the impact of different parasitic on the LNAs
  gain and noise figure.

4
Review of Gain and NF of a Receiver

• The power gain of a circuit is defined as
• The power gain in terms of voltage gain is
• The noise figure NF is a measure of the reduction
  in the signal to noise ratio in a circuit and is
  defined as

5
Review of Gain and NF of a Receiver

• The total gain of a receiver with n blocks is
  equal to
• The total NF of a receiver can be written as

Figure 1. Block diagram of n cascaded blocks.
6
Review of Gain and NF in a Receiver

• A low noise amplifier is usually the first active
  block after the antenna. It has a great impact on
  the performance of the receiver.

Figure 2. Block diagram of a receiver.
Maximum power transfer condition
Minimum noise figure condition
7
LNA Design Specification

• LNAs specifications are defined based on its
  targeted application (low voltage, low power,
  wide band, ultra low noise or high gain).

Parameter Acceptable Value
Noise Figure 2 dB
Power Gain 15 dB
IIP3 -10 dBm
Input Impedance (Z11) 50 ?
Input and output return loss (S11 S22) -10 dB
Reverse Isolation (S12) 20 dB
Stability Factor (K) gt 1
Table 1. Typical LNA specifications.
8
Common Source Cascode LNA

• A common source cascode LNA is mostly used in the
  industry. It has
• A common source cascode LNA can be considered as
  a two stage amplifier.
• If sizes of the devices and their operating
  points are selected properly, this LNA can
  achieve a good performance at low voltage and low
  power.

• Low Noise
• High Gain
• High Reverse Isolation.

• First Stage a Common Source
• Second Stage a Common Gate

Figure 3. Circuit diagram of a common source
cascode LNA.
9
LNAs Input Small Signal Model

• The gate-source capacitance, Cgs can be written
  as

Figure 4. Small signal equivalent circuit of the
input stage of the LNA.

• Rg is very small and can be ignored in the
  calculation of the input impedance. In the
  saturation region it can be written as
• gm is the transconductance factor of the
  transistor M1and in the saturation region can be
  written as

10
Review of Published Techniques

• Classical noise matching (CNM) technique
• Simultaneous noise and input matching (SNIM)
  technique
• Power constrained noise optimization (PCNO)
  technique
• Power constrained simultaneous noise and input
  matching (PCSNIM) technique

11
Classical Noise Matching Technique

• A matching circuit is placed between the source
  and input of the LNA.
• The matching circuit presents the optimum noise
  impedance Zopt to the LNA.
• A NF almost equal to the minimum noise figure
  (NFmin) of the active device can be achieved.
• There is an inherent mismatch between the Zopt
  and Zin.
• LNAs designed by the CNM technique offer lower
  gain.

Figure 5. Block diagram of the CNM technique.
12
Simultaneous Noise and Input Matching Technique

• Zopt is transferred in the Smith-Chart for better
  input matching.
• Different feedback techniques are proposed.
• An example of such circuits is an inductive
  source degenerated cascode LNA.
• The input impedance Zin is

Figure 6. A common source cascode LNA with source
inductor.
13
Simultaneous Noise and Input Matching Technique

• For small transistors (small Cgs), this technique
  suggests that the degeneration inductor has to be
  very large.
• At high RF frequencies (fgt5GHz), the effects of
  the gate-drain capacitance, Cgd must be
  considered as well.
• The impact of the bias circuitry in the input
  impedance must also be included.

14
Power Constrained Noise Optimization Technique

• A matching circuit is implemented in the input in
  addition to the source degeneration inductor.
• As the LNA power dissipation increases, the PCNO
  technique converges to SNIM. WHY?
• The quality factor of the gate inductor is not
  infinity. The resistance of the gate inductor
  adds the input noise.

Figure 7. Circuit diagram of a common source
cascode LNA with gate and source inductors.
15
Power Constrained Simultaneous Noise and Input
Matching Technique

• In addition to Lg, a capacitor Cex is added
  between gate and source.
• The size of source degeneration inductor LS can
  be reduced.
• Addition of the Cex in the input lowers the
  cutoff frequency fT.

Figure 8. Circuit diagram of a common source
cascode LNA with gate and source inductors and
extra capacitor between gate and source.
16
Impact of parasitic on the Gain and NF of a
Common Source LNA

• The reviewed methods provide a guideline in the
  design of a common source LNA for a certain power
  or noise figure.
• WORKING ENVIRONMENT LNA needs to work in
  different working environments (voltage,
  temperature and CORNERS).
• IMPACTS OF THE OTHER BLOCKS LNA may be
  implemented on-chip with other blocks such as
  voltage controlled oscillators (VCOs) and mixers.
  
• PADS are required to connect the LNA to the
  package/board.
• LNA needs to have an ELECTRO-STATIC DISCHARGE
  (ESD) protection.
• WIRE BONDS are required to connect the IC to the
  package.
• Some kind of PACKAGING is required for the
  industrial use.

17
Working Environment

• Voltage requirements
• Temperature requirements
• Corner requirements
• Fast-Fast and Slow-Slow corners must be checked
  in the design stage as well.

Figure 10. Picture of a test set up for the
corner test of an IBM SiGe wafer.
18
Impacts of the other Blocks
Figure 11. Cross sections of two blocks on IC.

• CMOS substrate presents
• high-resistivity in depth.
• lower-resistivity in surface.

19
Pads and ESD diodes
Figure 12. Layout diagram of a LNA in ST 90nm
CMOS technology.
Figure 13. Layout diagram of a current mirror
with pad connection for wafer probing.

• In some design technologies pads have all the
  metal layers. In others they may have only the
  last two metal layers. WHY NOT ONLY LAST LAYER?
• The last metal layers have less capacitance to
  the substrate.
• The pad dimensions and structure are determined
  by reliability issues and manufacturing margin
  for wire bonding.

Figure 14. Electrical equivalent circuit of a pad.
20
Pads and ESD diodes

• An integrated circuit (IC) connected to external
  ports is susceptible to damaging electrostatic
  discharge (ESD) pulses from the operating
  environment and peripherals.
• Each pad on IC must be protected by ESD diodes
  for reliability reasons and ease of handling.
• The use of ESD protection involves three main
  issues
• 1) A large capacitor from the node to the
  ground or VDD.
• 2) Coupling of noise from VDD to the input of
  the circuit.
• 3) Latch-up in CMOS circuits during normal
  operation.

mm
Figure 15. Simple ESD protection circuit.
21
Wire Bonds and Package Parasitic
Figure 17. Different samples of packaged ICs.
Figure 16. Bonding diagram of an IC on a 48 pin
QFN package.

• Some IC manufacturers such as IBM use FLIP-CHIP
  in some products instead of wire bonding.
• FLIP-CHIP ICs do not have the wire bonds
  parasitic.

22
Matching and Board Parasitic

• The printed circuit board has parasitic
  capacitor and inductor as well. A long thin track
  will be inductive and a large pad over the ground
  plane will be capacitive.
• On board matching components, such as capacitors
  are not ideal.

Figure 19. Board layout diagram of an IC with 48
I/O pins.
Figure 18. Equivalent circuit of a surface
mounted capacitor on a PCB with ground plane.
23
Summary of Different Parasitic
Where are the parasitic components?

• ESD diodes
• Pads
• Wire bonds
• Package
• Matching Circuit
• Printed Circuit Board

Board Level
Silicon Level
Package Level
24
Cascode LNA with ESD Diodes

• Current mirror transistor (M3) sets the current
  of the LNA.
• ESD diodes are added to the input, output, ground
  and VDD pads. OUTPUT PAD?
• Equivalent impedance of the pad is shown as a
  small capacitor.
• Different ESD diodes are used for the I/O, VDD
  and ground pads.

Iin
Iout
Figure 20. Circuit diagram of a cascode LNA.
25
Cascode LNA with ESD Diodes
Figure 21. Circuit diagram of the input stage of
the LNA with pads and ESD diodes.

• The input impedance of the LNA with pad parasitic
  is equal to

26
Equivalent Circuit Diagram of the LNA with Wire
bonds
Figure 23. LNA with Wire bonds.
Figure 22. Sample IC with 12 LNAs.

• A mutual inductance exists between every one of
  these inductors.
• The mutual inductances depend on the location of
  the pads on the chip, the spacing between them
  and also the physical angle between the wire
  bonds.

27
Input Impedance of the LNA with Wire Bonds and
pads
Figure 24. Circuit diagram of input stage of the
LNA with ESD diodes, pads and wire bonds.
28
Quad Flat Nonleaded Package Electrical Model

• There are capacitors between pins and
  lead-frames to the ground plane.
• Mutual inductances between the neighboring pins
  and pins that are one step further apart.
• Equivalent electrical model of the ground of the
  pin and the ground of the package.

Figure 25. Electrical model of Quad-Flat-Nonleaded
(QFN) package.
29
Input Impedance with QFN Package
Figure 26. Circuit diagram of input stage of the
LNA with ESD diodes, pads, wire bonds and
package.
30
Transconductance and gain of the first stage of
the LNA
Figure 27. Block diagram of a cascode LNA.

• A cascode LNA can be treated as two cascaded
  amplifiers.
• The voltage gain of a common source stage without
  parasitic is

Figure 28. TOP A common source stage. BOTTOM
Low frequency small signal model.
31
Transconductance and gain of the first stage of
the LNA

• The voltage gain of the common source stage with
  parasitic (ignoring the Cp1) is

• The transconductance of the common source stage
  with parasitic is

32
Noise Figure
Gate Resistance Thermal Noise
Load Equivalent Resistance Thermal Noise
Source Resistance Thermal Noise
Figure 29. Small signal equivalent circuit of a
common source amplifier for noise analysis.

• Gate Resistor Thermal Noise
• Channel Thermal Noise
• Gate Current Noise

Output Noise
33
Noise Figure
Figure 30. Equivalent circuit of the input stage
of the LNA with noise sources.
34
Experimental Results
No. ESD diodes in the input pad Noise Figure (dB) Gain (dB)
1 1.8 18.57
2 2.13 17.54
3 2.58 16.38
4 3.12 15.28
5 3.71 14.25
6 4.33 13.17
7 4.96 12.24
8 5.58 11.41
Table 2. Measured NF and Gain vs. Number of ESD
diodes in the Input.
Figure 31. Measured variation of NF and gain with
number of ESD diodes for a 1.5 GHz cascode LNA.
35
Experimental Results
Gain (dB) Gain (dB) Noise Figure (dB) Noise Figure (dB)
Total Current (mA) Without Parasitic With Parasitic Without Parasitic With Parasitic
3.5 16.39 14.23 0.86 1.84
4.7 16.46 14.61 0.92 1.76
5.9 18.17 15.32 0.77 1.72
7.1 18.42 16.21 0.73 1.52
8.1 18.69 16.77 0.72 1.47
9.2 18.9 16.82 0.72 1.47

Table 3. Simulated gain and NF of a 1.5 GHz
cascode LNA at 1.8 V without and with pad, ESD,
wire-bond and package parasitic.
36
Conclusions

• The parasitic impact the gain and NF of the LNA.
• The gain can be reduced by as much as 15 and the
  NF can worsen up to 200 due to parasitic.
• The published LNA gain and NF optimization
  techniques can not be used for ESD protected,
  wire bonded and packed LNAs.
• On-chip matching of the LNA must be done with
  consideration of pads, ESD diodes, wire bonds and
  package parasitic.

37
Acknowledgements
Thank you to all of my teachers that thought me
the material presented here over the years.