Introduction to CMOS VLSI Design Lecture 4: DC

1
Introduction toCMOS VLSIDesignLecture 4 DC
Transient Response

• Greco/Cin-UFPE
• (Material taken/adapted from Harris lecture
  notes)

2
Outline

• DC Response
• Logic Levels and Noise Margins
• Transient Response
• Delay Estimation

3
Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

4
Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

5
DC Response

• DC Response Vout vs. Vin for a gate
• Ex Inverter
• When Vin 0 -gt Vout VDD
• When Vin VDD -gt Vout 0
• In between, Vout depends on
• transistor size and current
• By KCL, must settle such that
• Idsn Idsp
• We could solve equations
• But graphical solution gives more insight

6
Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vgsn gt Vdsn lt Vgsn gt Vdsn gt
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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vgsn gt Vtn Vdsn lt Vgsn Vtn Vgsn gt Vtn Vdsn gt Vgsn Vtn
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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vgsn gt Vtn Vdsn lt Vgsn Vtn Vgsn gt Vtn Vdsn gt Vgsn Vtn
Vgsn Vin Vdsn Vout
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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vin lt Vtn Vgsn gt Vtn Vin gt Vtn Vdsn lt Vgsn Vtn Vout lt Vin - Vtn Vgsn gt Vtn Vin gt Vtn Vdsn gt Vgsn Vtn Vout gt Vin - Vtn
Vgsn Vin Vdsn Vout
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vgsp lt Vdsp gt Vgsp lt Vdsp lt
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vgsp lt Vtp Vdsp gt Vgsp Vtp Vgsp lt Vtp Vdsp lt Vgsp Vtp
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vgsp lt Vtp Vdsp gt Vgsp Vtp Vgsp lt Vtp Vdsp lt Vgsp Vtp
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vin gt VDD Vtp Vgsp lt Vtp Vin lt VDD Vtp Vdsp gt Vgsp Vtp Vout gt Vin - Vtp Vgsp lt Vtp Vin lt VDD Vtp Vdsp lt Vgsp Vtp Vout lt Vin - Vtp
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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I-V Characteristics

• Make pMOS is wider than nMOS such that bn bp

16
Current vs. Vout, Vin
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Load Line Analysis

• For a given Vin
• Plot Idsn, Idsp vs. Vout
• Vout must be where currents are equal in

18
Load Line Analysis

• Vin 0

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Load Line Analysis

• Vin 0.2VDD

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Load Line Analysis

• Vin 0.4VDD

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Load Line Analysis

• Vin 0.6VDD

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Load Line Analysis

• Vin 0.8VDD

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Load Line Analysis

• Vin VDD

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Load Line Summary
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DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

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Operating Regions

• Revisit transistor operating regions

Region nMOS pMOS
A
B
C
D
E
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Operating Regions

• Revisit transistor operating regions

Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
28
Beta Ratio

• If bp / bn ? 1, switching point will move from
  VDD/2
• Called skewed gate
• Other gates collapse into equivalent inverter

29
Noise Margins

• How much noise can a gate input see before it
  does not recognize the input?

30

• By definition, VIH and VIL are the operational
  points of the inverter where

A high gain (g) is desirable
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Logic Levels

• To maximize noise margins, select logic levels at

32
Logic Levels

• To maximize noise margins, select logic levels at
  
• unity gain point of DC transfer characteristic

33
Transient Response

• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t)
  changes
• Requires solving differential equations
• Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa

34
Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

40
Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2 (upper
  bound)
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
  (upper bound)
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time
• time required for a node to charge from the 10
  point to 90 ( 0.1 VDD to 0.9 VDD )
• tf fall time
• time required for a node to discharge from 90 to
  10 point (0.9 VDD to 0.1 VDD )

41
Delay Definitions
Tpdr TpHL
Tcdf TpHL
tf
tr
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CMOS Inverter Switching Characteristics

• Define
• Falling delay tdf delay time with output
  falling
• Rising delay tdr delay time with output rising

43
Trajectory of a n-transistor operating point
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Fall-time equivalent circuit
Rise-time equivalent circuit
The fall-time is faster than the rise time,
tftr/2 primarily due to different
carrier mobilities associated with the p and n-
devices µn 2 µp It is true
considering equally sized n and p transistors
ßn 2 ßp
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Trajectory of a n-transistor operating point

• If the designer wants to have both n an p
  transistor with the same rise and fall time
• ßn / ßp 1
• This implies that channel width for the p-device
  must be increased to approximately two to three
  times of the n-device
• wp 2 3 wn

46
Delay Estimation

• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask What if?
• The step response usually looks like a 1st order
  RC response with a decaying exponential.
• Use RC delay models to estimate delay
• C total capacitance on output node
• Use effective resistance R
• So that tpd RC
• Characterize transistors by finding their
  effective R
• Depends on average current as gate switches

47
RC Delay Models

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

Resistance inversely proportional to width
pMOS
nMOS
Capacitance proportional to width
48
RC Delay Models

• Resistance of a uniform slab
• R ? (l/A) (?/t) (L/W) where ? is the
  resistivity in ohm-cm, t is the thickness in cm,
  L is the length, W is the width, and A is the
  cross-sectional area
• Using the concept of sheet resistance, R
  Rs (L/W) where Rs is called the sheet
  resistance and given in ohms per square
• Rs ? / t
• Gate Capacitance
• -

Cg eoxWL/tox eoxA/tox
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MOS device capacitances

• MOS Device capacitances
• Cgs, Cgd gate-to-channel capacitances, which
  are lumped at the source and the drain regions.
• Csb, Cdb source and drain-duiffusion
  capacitances to bulk (or substrate)
• Cgb gate to-bulk capacitance

50
MOS device capacitances
1. Off region, where Vgs lt Vt. There is no
channel Cgs, Cgd 0. 2. Non-saturated region,
where Vgs - Vt. gt Vds. Cgb 0 3. Saturated
region, where Vgs lt-Vt. lt Vds. Channel is
heavely inverted. The drain is pinched off
causing Cgd 0.
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RC Delay Models
pMOS capacitance 2x nMOS capacitance
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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

58
Elmore Delay

• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

59
Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

60
Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

62
Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

63
Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

Rising time nMOS - off
pMOS - on
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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

Consider that the nMOS resistance (pMOS
resistance)/2 R/2
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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Delay Components

• Delay has two parts
• Parasitic delay
• 6 or 7 RC
• Independent of load
• Effort delay
• 4h RC
• Proportional to load capacitance

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Contamination Delay

• Best-case (contamination) delay can be
  substantially less than propagation delay.
• Ex If both inputs fall simultaneously

70
Diffusion Capacitance

• we assumed contacted diffusion on every
  source/drain
• Good layout minimizes diffusion area
• Ex NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too

71
Layout Comparison

• Which layout is better?