Testing in the Fourth Dimension

1
The Remarkables, Frankton, New Zealand, Near Lake
Alta (Dimrill Dale)
2
Dart and Rees River Delta, Paradise, New Zealand
(The Wizards Vale)
3
332479 Concepts in VLSIDesignLecture 2Trends
in ULSI Technology for the Next 15 Years

• Michael L. Bushnell
• Center for Advanced Information Processing
• and Wireless Information Networks Lab.
• ECE Dept., Rutgers University
• Piscataway, New Jersey, USA

4

• Material from
• Essentials of Electronic Testing for Digital,
  Memory Mixed-
• Signal VLSI Circuits, by Bushnell Agrawal,
  Kluwer Academic Pub., 2000
• International Technology Roadmap for
  Semiconductors,
• Semiconductor Industry Association, 2001, 2002
  updates
• Low-Power CMOS VLSI Circuit Design, by Roy and
  Prasad, Wiley-Interscience, 2000
• Principles of CMOS VLSI Design, by Weste and
  Harris, Addison-Wesley, 2005

5
Outline

• Introduction Where We Are
• Systems-on-a-Chip (SoC)
• Systems-in-a-Package (SIP)
• Key Problems from the International Technology
  Roadmap for Semiconductors with Ultra Large Scale
  IC Technology
• Low-Power Design and Batteries
• Lithography
• Metrology
• Testing
• Materials
• Commercial Possibilities
• Conclusions

6
Gordon Moores Law (1969)

• Two components
• Transistor dimensions reduce by 10.5 every year
• Density increases 22.1 every year
• Additional 22 increase every year due to
• Wafer and chip size increases
• Circuit design and fabrication process
  innovations
• 44 transistor count increase in microprocessors
  every year
• Transistor count more than doubles every 2 years

7
Moores Law in Action
8
Exponential Trend in Clock Rate
9
System-on-a-Chip (SoC)

• A single chip replaces the whole PCB (Printed
  Circuit Board)
• Different chips on PCB are now building blocks
  (cores) of SoC chip
• Advantages
• On-chip interconnects are many times faster than
  off-chip wires
• Get a compact system with the same functionality
• Reduces pin overhead
• Saves much power
• Reduces noise in the mixed-signal/analog circuits
• Liabilities
• Bed-of-nails (decomposition) system testing is
  not possible
• Most of the cores are surrounded by many other
  cores
• Results in very poor controllability and
  observability
• Need electronic test hardware to access these
  blocks during testing

10
Example System-on-a-Chip
11
System-in-a-Package (SIP)

• SoC technology a great success, EXCEPT for
  radio receiver/transmitters
• Can sustain mixed analog/digital hardware
  together on one chip, provided that
• Analog hardware is in the voice band
• Digital clocks their harmonics are carefully
  chosen to avoid polluting key parts of the
  spectrum with noise
• Key result Still unable to integrate radio
  frequency (RF) hardware into SoC
• Substrate coupling between digital and analog
  parts causes digital clock noise to destroy the
  signal-to-noise ratio of RF part
• RF tuners still require precision inductors, but
  on-chip inductors are expensive and inadequate
• Interim solution Combine separate digital
  analog chips and passive components into a single
  package

12
Key Conclusions Grand Challenges

• Silicon CMOS process will experience more
  aggressive scaling in reducing feature sizes than
  before
• In order to maintain Moores Law
• Reaching fundamental limits of materials for the
  planar silicon CMOS process
• Continue for only 5-10 years more with new
  materials
• Need new, non-CMOS devices (i.e., transistor
  replacement)
• No known solutions for most technical problems of
  silicon CMOS after 2005-2007

13
Long-Term Trends

• IC market growth averaged 17 per year
• CMOS circuits represent more than 75 of the
  worlds semiconductors
• 16 annual chip feature size reduction 1995-2001
• 11 annual chip feature size reduction 2002
  future
• DRAM chip size increases 12 / year
• Pins/balls on packages increase 10 / year
• Pin cost decreases 5 / year
• Average package cost increases 5 / year
• Packaging share of system cost doubles over 15
  years
• Drives migration to SoC, Multi-Chip Modules
  (MCMs), or SIP devices

14
VLSI Technology Trends

• Source International Technology Roadmap for
  Semiconductors Semiconductor Industry
  Association
• NSF, NIST, Depts. of Commerce, Defense, Energy,
  Semiconductor Research Corporation, SEMATECH
• Assumptions
• Moores Law continues to hold
• DRAM bit count goes up 4 times every 3 yrs. to
  2010
• Si CMOS -- gt 75 of worlds semiconductors

15
Economic Conclusions

• By 2010
• Memory costs 1/20 what it costs today
• Microprocessors are 10 times faster
• By 2016
• Memory cost less than 1/100 todays prices
• Microprocessors are 15 times faster
• Industry conclusions
• Need increased support for University research
• Got 8 increase in NSF appropriations for 2002
• Industry funding agencies
• National Nanotechnology Initiative
• Networking and Information Technology Research
  Initiative
• Defense Depts. Government Industry Cooperative
  University Research Program

16
Surprise Scaling Faster than Ever!

• History of 30 per-year per-function cost
  reduction
• 0.7 feature scaling from generation to next
• 1995 expected Moores law to end in 2010 with
  0.1 mm feature size looks like it will continue
  until we hit 0.01 mm!
• Chip cost kept increasing, but customer
  cost/benefit per function kept dropping
• Multi-chip modules (MCMs) took over from
  printed circuit boards (PCBs) in many
  applications
• Systems-on-a-chip (SoCs) single chip entire
  system with sensor, wireless receiver/transmitter,
  mprocessor, digital signal processor (DSP), and
  memory
• Starting to take over from MCMs

17
Shrinking Feature Sizes

• MPU means microprocessor

18
DRAM Characteristics
19
High-Performance mProcessor Characteristics at
Introduction Year
20
Numbers of Pads per Chip
21
Wiring Levels and Mask Levels
22
On-Chip Clock f and Power Supply VDD
23
Power Dissipation
24
mProcessor and DRAM Fault Density Targets
25
Silicon, Packaging, and Test Costs

• Flat test cost drives migration to built-in
  self-test

26
Low-Power Design

• Off-power of chips increases 10 times each time
  we shrink to a new feature size (some say 20
  times)
• Power dissipation for high-performance
  mprocessors will exceed package limits by 25
  times in 15 years
• MOSFET Transistor Leakage
• Need to control gate leakage
• Need to control sub-threshold leakage
• Switch to very thin high-k oxynitride dielectric
  for gate oxide around 2005
• Switch to metal transistor gate from polysilicon
  gate

27
Transistor Leakages

• I1 pn Reverse-Bias Current
• I2 Weak Inversion
• I3 Drain-Induced Barrier-Lowering
• I4 Gate-Induced Drain Leakage

• I5 -- Punchthrough
• I6 Narrow-Width Effect
• I7 Gate Oxide Tunneling
• I8 Hot-Carrier Injection

28
Low-Power Design

• Interim solutions
• Use multiple transistor thresholds (Vt) on one
  chip
• Use multiple oxide thicknesses (tox) on one chip
• Use multiple power supplies (VDD) on one chip
• Very slow VDD scaling hard technical problem
• ULSI Power Management
• Switch to lower clock f when less computing
  needed
• Selectively power down unused parts of chip
• Redesign DSP and mprocessor data path to use less
  energy
• Power supply signal noise sensitivity
  increasing
• Operating voltage decreases 20 for each feature
  size shrink

29
FD and DGDT Silicon-On-Insulator MOSFETs

• Need to be integrated onto the same chip as
  traditional CMOS devices could save much power

30
Low-Power Design and Batteries

• At present, NiCd batteries provide 120 Watt Hrs /
  Kg
• Improvements come extremely slowly

31
Optical Lithography

• Optical lithography has steadily growing cost and
  fails after 2010 (45 nanometer feature size and
  below)
• Main problem is diffraction forces us to
  higher-energy light
• Difficult to make masks for lithography more
  expensive ASICs
• Higher cost due to limited exposure field
• As we increase f of light, lens materials become
  opaque
• In 2003, critical dimension control fails to meet
  requirements

32
Lithography Using SiO2
33
Potential Long-term Replacements

• Extreme ultra-violet lithography ArF and F2
• Most developed solution, but requires reflective
  optics and Megawatt laser
• Electron projection lithography slower than
  present method
• Proximity electron lithography difficulties in
  mask making
• Proximity X-ray lithography requires a
  synchrotron
• Ion projection lithography
• Maskless lithography electron beam lithography
  too slow
• Nano-imprint lithography cheap (U. of
  Canterbury)
• Evanescent near-field lithography cheap (U. of
  Canterbury)

34
Lithography Near Term

• Want to increase f and shorten wavelength of
  light for lithography to control diffraction
  progress to extreme ultra-violet light - l 248
  (Xe) to 193 (ArF) to 157 (F2) nanometer light
• Need new photo-resists for l 193 to 157
  nanometer light
• Need new optical lens materials present-day
  materials become opaque to higher-energy light
• CaF2 is new lens material
• Need to use optical proximity corrections and
  phase shifting masks
• Must use off-axis illumination
• Control of line edge roughness is a problem
  during etching
• Need improvements to control mask damage due to
  electro-static discharge

35
Lithography Field Sizes
36
Lithography Long Term

• Cost of making masks for lithography drastically
  increasing
• Need 9 nanometer control for solid line critical
  dimensions (CD)
• Need 14 nanometer control for contact CD
• Need to control transistor gate line widths to 3
  nanometers
• Need a totally new exposure concept
• Electron Projection Lithography uses very thin
  membranes, which are a very different mask
  concept from present-day glass plates, covered
  with Cr
• Photo-resist materials start failing in 2004 due
  to defects and line edge roughness

37
Metrology Ability to Measure

• Need new, non-destructive measurement techniques
  for electron microscopy and atomic force
  microscopy
• Must deal with 3-dimensional structures and their
  defects
• Need to measure better these properties
• Voids and pores in Cu wiring
• Impurity particles present in semiconductor
  materials
• Control of high aspect-ratio technologies, such
  as dual-Damascene process
• Interfacial properties (physical and electrical)
  of new gate and capacitor dielectrics, and new
  thin-film materials

38
Failure Analysis

• Hard to analyze circuit failures that leave no
  detectable physical remnant, but only cause
  electrical anomaly

39
Present Testing Method

• Build hardware test busses between all memories,
  digital circuits, and analog circuits
• Use built-in self-test to test memories
• Testing procedure
• Test scan chains and test bus for correct
  function
• Test digital hardware independently of
  analog/memory hardware using scan chains
• Test memory hardware
• Test analog hardware independently of other
  hardware using analog test bus
• Test interconnections between digital/analog/memor
  y hardware

40
ADVANTEST Model T6682 1 GHz Automatic Test
Equipment
41
Testing Problems

• Introducing extremely high-speed digital device
  interfaces to speed up packet switching
• Requires test equipment probes with high f and
  high pin counts extremely costly
• Requires clock jitter analysis for high-speed
  serial interfaces
• Requires added hardware for design-for-testability
  (DFT)
• Need new electrical tests for ultra-thin
  transistor gates and new dielectric materials for
  capacitors

42
Testing Problems of SoCs

• Parts of the chip use DFT and built-in self-test
  (BIST)
• Urgently need better research on analog DFT and
  analog BIST
• Radio frequency (RF) test with large and noisy
  digital circuits is not yet possible
• Substrate coupling between digital and RF parts
  of chip destroys signal-to-noise ratio of analog
  circuits
• Need better schemes for reusing test mechanisms
  for embedded cores
• Still must keep RF part on a separate chip

43
Basic Principle of IDDQ Testing

• Measure IDDQ current through Vss bus

44
Problem with IDDQ Testing

• Background leakage currents of transistors
  increase 10 to 20 times for each feature size
  scaling
• IDDQ test greatly increased defect detection
  capability, since it finds shorts and some opens
  that voltage test cannot find
• Burn-in captures infant mortality failures of new
  chips
• Problem with small feature sizes and thermal
  runaways
• Need replacements for both methods
• Noise-based graphical IDDQ test (Rutgers U.)

45
Fault Modeling for Testing

• Need new fault models and testing methods for new
  nanotechnology devices
• Sensors integrated with digital and analog
  circuits on silicon
• Heterostructures semiconductor devices with pn
  junctions made from multiple materials
• New kinds of transistors (non-CMOS)
• Vertical MOSFET and thin-film transistors
• Micro Electro-Mechanical System (MEMS) devices
  integrated on chip
• Single-electron transistors
• Carbon Nano-tubes
• Quantum-Dot Devices

46
Fault Tolerance

• Testing costs and manufacturing costs are
  steadily increasing
• Consider abandoning requirement that all
  transistors and wires work perfectly on the chip
• Exploring adaptive and self-correcting/self-repair
  ing circuits
• Promise a cost reduction for design verification,
  manufacturing, and testing

47
Scaling Problems

• Need a new transistor gate stack material to
  continue scaling tox (gate oxide thickness) below
  2 nanometers
• Allows shorter gate length, smaller gate stack,
  shallower drain junction depths
• Allows thinner gate oxide
• Need a new transistor gate material replace
  polysilicon with multiple metals

48
New Starting Materials

• Industry just switched to 300 mm diameter silicon
  wafers from 150 mm diameter wafers
• Huge improvement in mass production efficiency
• Want to go to 450 mm diameter silicon wafers in
  the future
• Not clear that Czochralski ingot-pulling process
  is capable of this

49
Czochralski Ingot Growth Furnace
50
Commercial Possibilities

• What do we do with all of this cheap hardware?
• Make it mobile
• Put a radio receiver/transmitter on every chip
• Make it sense DNA
• Put a chip on everything
• Keep the cost really low
• Make it ultra-reliable and self-testing
• Keep the power low
• Battery technology hardly improves at all over
  time

51
Mobile Sensors on Silicon

• Complete chip with radio receiver/transmitter,
  mprocessor, memory, DSP unit, sensors, and analog
  conditioning electronics
• Can be mounted on mobile or stationary devices
• Create an ad-hoc network, where sensors relay
  information through neighborhood forwarding nodes
• Applications
• Counter-terrorism, bridge/highway inspection,
  medical monitoring of patients, pollution
  monitoring

52
RF Tagged Objects

• Coming into use now for certain cost-effective
  applications
• Allows tagging of objects with wireless sensors
• Makes it easy to keep track of the objects

53
DNA Chips, Biological Sensors/Activators

• Chip with sensor
• Takes tissue/blood samples from patient
• Analyzes DNA looks for
• DNA fingerprint of individual
• Genetic structure and genetic defects
• Analyzes blood, such as glucose level, white cell
  count, etc.

54
Conclusions

• ULSI technology advanced much faster than anyone
  expected
• Result Will start hitting fundamental limits of
  silicon CMOS process starting in 2005
• Excessive power consumption
• Lithography will fail
• Measurement problems at the atomic level
• Exorbitant testing costs
• Material problems
• Moores Law is slowing
• These limits will usher in a new era of different
  MOS devices (SOI) and nanotechnology in an
  attempt to keep Moores Law going

55
ULSI Past, Present, Future
56
Optical Testing

• Dual-Damascene process creates deep trenches
  between metal wires
• Problem with optical defect detection in these
  trenches
• Via defects near or at the trench/via bottom are
  missed
• Must optically examine wafer after each
  processing step
• Otherwise, next layer of material hides defect in
  lower layer
• Problem with void detection in copper wires
• Problem with pore size distribution in patterned
  low k dielectrics

57
Design Productivity Problems

• Must scale at same rate as design complexity, or
  cost goes up
• Currently being solved by design reuse and
  intellectual property cores
• Problem with analog and mixed-signal design,
  verification and testing
• Need enhanced software productivity, since
  significant embedded software is now on chip

58
On-Chip Interconnections

• Difficulties in depositing metal into deep
  narrow holes on chip surface for wiring
• Need a better barrier metal prevents wiring
  metal from interacting with silicon
• Need a better wiring material has little
  interaction between wiring and insulator layers
• Must fill contact holes with high aspect ratio
• Optical, wireless, or microwave interconnect
  needed

59
DRAMs

• Constantly need to reduce cell area on chip to
  increase memory size on chip
• Ccell 25 to 35 fF for reliable operation
• Need to increase ratio of C area / chip area
• Requires materials with higher k
• Change from Silicon-Insulator-Silicon (SIS)
  capacitors to Metal-Insulator-Metal (MIM)
  capacitors

60
Nanotechnology

• Nanotechnology has arrived (chip features less
  than 0.1 mm)
• No cost-effective way to make such tiny patterns
• High energy ultra-violet light, narrow spectrum
  X-rays, electron-beam lithography being explored,
  nano-imprint technology, molecular clustering
• Used with Micro Electro-Mechanical Machines
  (MEMS) devices on chip
• Mechanical sensors (accelerometers) automobile
  air-bag sensor
• Sensors are now on the Silicon
• Photonic sensors and interconnects
• DNA sensors
• Biochemical sensors
• Chemical sensors
• Surface Acoustic Wave filters (Radio Frequency
  transmission/reception)

61
Impact on Designers

• Reduced supply voltage 5 V 3.3 V
  2.5 V 1.1 V
• 2-input NAND gate delay used to be 1-2 nsec is
  now 160 psec
• Density transistor count on chip went from 8
  million to 55 million (heading towards 1 billion)
• Fall 1991 VLSI class designed a ½ billion
  transistor DRAM
• Systems-on-a-Chip are reality
• Learn Analog VLSI Design
• Learn to design sensors
• Learn to design RF receiver transmitters
• Learn to design DRAM and SRAM on your chip
• Core-based design is now the mainstream

62
Fabulous Research Areas

• Nanotechnology (Rutgers Nanotechnology Center)
• Wireless Systems-on-a-Chip (WINLAB MUSE Project)
• Low-Power Design (WINLAB MUSE Project)
• VLSI Testing (CAIP Testing Project)
• VLSI System Architectures (WINLAB MUSE Project)
• Hardware/Software Co-Design
• Sensors on Silicon (WINLAB MUSE Project)
• Formal Hardware Verification

63
Summary

• Moores Law
• SoC and SIP
• Grand Challenges
• Feature Sizes, Power, Wiring Levels, and Clock
  Speed
• Low-Power Design and Batteries
• Lithography
• Testing
• Fault-Tolerance
• Scaling
• Applications