ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic Devices

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ECE2030 Introduction to Computer
EngineeringLecture 17 Memory and Programmable
Logic
Prof. Hsien-Hsin Sean Lee School of Electrical
and Computer Engineering Georgia Tech
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Memory

• Random Access Memory (RAM)
• Contrary to Serial Access Memory (e.g. Tape)
• Static Random Access Memory (SRAM)
• Data stored so long as Vdd is applied
• 6-transistors per cell
• Faster
• Differential
• Dynamic Random Access Memory (DRAM)
• Require periodic refresh
• Smaller (can be implemented with 1 or 3
  transistor)
• Slower
• Single-Ended
• Can be read and written
• Typically, addressable at byte granularity
• Read-Only Memory (ROM)

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Block Diagram of Memory
N-bit Data Input (for Write)
N
K-bit address lines
Memory Unit
K
2k words N-bit per word
Chip Enable
N-bit Data Output (for Read)
N

• Example 2MB memory, byte-addressable
• N 8 (because of byte-addressability)
• K 21 (1 word 8-bit)

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Static Random Access Memory (SRAM)
Wordline (WL)
BitLine

• Typically each bit is implemented with 6
  transistors (6T SRAM Cell)
• During read, the bitline and its inverse are
  precharged to Vdd (1) before set WL1
• During write, put the value on Bitline and its
  inverse on Bitline_bar before set WL1

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Dynamic Random Access Memory (DRAM)
Wordline (WL)
Bitline

• 1-transistor DRAM cell
• During a write, put value on bitline and then set
  WL1
• During a read, precharge bitline to Vdd (1)
  before assert WL to 1
• Storage decays, thus requires periodic refreshing
  (read-sense-write)

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Memory Description

• Capacity of a memory is described as
• addresses x Word size
• Examples

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How to Address Memory
4x8 Memory
2-to-4 Decoder
0
A0
1
2
A1
3
CS
Chip Select
D7
D6
D5
D4
D3
D2
D1
D0
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How to Address Memory
4x8 Memory
2-to-4 Decoder
0
A01
1
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
2
A10
3
CS
Chip Select1
D7
D6
D5
D4
D3
D2
D1
D0
Access address 0x1
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Use 2 Decoders
8x4 Memory
2-to-4 Decoder Row Decoder
0
A1
1
2
A2
3
CS
Tristate Buffer (read)
D0
D1
D2
D3
0
1
Chip Select
CS
1-to-2 Decoder Column Decoder
A0
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Tristate Buffer
En
Input
Output

• Similar to Transmission Gate
• Could amplify signal (in contrast to a TG)
• Typically used for signal traveling, e.g. bus

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Bi-directional Bus using Tri-state Buffer
Direction (control data flow for read/write)
A
Input/Output
B
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Read/Write Memory
8x4 Memory
0
A1
1
2-to-4 Row Decoder
2
A2
3
CS
D0
D1
D2
D3
0
1
Chip Select 0
CS
1-to-2 Column Decoder
A0
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Read/Write Memory
8x4 Memory
0
A1
1
2-to-4 Row Decoder
2
A2
3
CS
D0
D1
D2
D3
0
1
Chip Select 1
CS
1-to-2 Column Decoder
A0
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Building Memory in Hierarchy

• Design a 1Mx8 using 1Mx4 memory chips

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Building Memory in Hierarchy

• Design a 2Mx4 using 1Mx4 memory chips

Note that 1-to-2 decoder is the wire itself (or
use an inverter)
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Building Memory in Hierarchy

• Design a 2Mx8 using 1Mx4 memory chips

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Memory Model

• 32-bit address space can address up to 4GB (232)
  different memory locations

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Endianness Danny Cohen 91

• Byte ordering ? How a multiple byte data word
  stored in memory
• Endianness (from Gullivers Travels)
• Big Endian
• Most significant byte of a multi-byte word is
  stored at the lowest memory address
• e.g. Sun Sparc, PowerPC
• Little Endian
• Least significant byte of a multi-byte word is
  stored at the lowest memory address
• e.g. Intel x86
• Some embedded DSP processors would support both
  for interoperability

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Endianness Examples

• Store 0x87654321 at address 0x0000,
  byte-addressable

Lower Memory Address
Lower Memory Address
0x87
0x21
0x0000
0x0000
0x65
0x43
0x0001
0x0001
0x43
0x65
0x0002
0x0002
0x21
0x87
0x0003
0x0003
Higher Memory Address
Higher Memory Address
BIG ENDIAN
LITTLE ENDIAN
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Memory Allocation (Little Endian)
.data .globl declare declare .align
0 .word 511 .byte 14 .align 2 .byte
14 .word 0x0B1E8143 .align 2 .ascii
GAece .half 10 .word 0x2B1E8145 .space
1 .byte 52 .align 1 .byte 16 .space 2 .byte
67
0xFF
------
0x34
e
0
1c
0x01
------
------
f
1d
1
0x00
0x10
0x47
1e
2
10
0x00
0x41
3
11
1f
0x0E
0x65
4
20
12
------
0x63
0x43
13
5
21
------
0x65
6
14
.align N Align next datum on a 2n byte
boundary .align 0 turn off automatic alignment
for .half, .word, .float, and .double till
the next .data directive .word 4 bytes .half
2 bytes .byte 1 byte .space 1-byte
space .ascii ASCII code (American Standard Code
for Information Interchange)
------
0x0A
15
7
0x0E
0x00
16
8
0x43
0x45
9
17
0x81
0x81
a
18
0x1E
0x1E
b
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0x0B
0x2B
1a
c
------
d
1b
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Read Only Memory (ROM)

• Permanent binary information is stored
• Non-volatile memory
• Power off does not erase information stored

ROM
K-bit address lines
N-bit Data Output
2k words N-bit per work
K
N
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32x8 ROM
32x8 ROM
8
5
Each represents 32 wires
0
A4
1
2
A3
5-to-32 Decoder
3
A2
A1
28
29
A0
30
31
Fuse can be implemented as a diode or a pass
transistor
D1
D0
D7
D6
D5
D4
D3
D2
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Programming the 32x8 ROM
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Example Lookup Table

• Design a square lookup table for F(X) X2 using
  ROM

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Square Lookup Table using ROM
0
1
X2
2
3-to-8 Decoder
3
X1
4
X0
5
6
7
F1
F0
F5
F4
F3
F2
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Square Lookup Table using ROM
0
1
X2
2
3-to-8 Decoder
3
X1
4
X0
5
6
7
F1
F0
F5
F4
F3
F2
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Square Lookup Table using ROM
0
1
X2
2
3-to-8 Decoder
3
X1
4
X0
5
6
7
F0
F1
F5
F4
F3
F2
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Classifying Three Basic PLDs
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Programmable Logic Array (PLA)
A
Programmable OR Plane
B
C
Programmable AND Plane
C
C
B
B
A
A
F2
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Example using PLA
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Example using PLA
A
B
C
AB
C
C
B
B
A
A
F1
F2
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PAL Device
IO1
IO1
IO1
IO2
B
B
A
A
IO1
Programmable AND Plane
A
IO2
B
Fixed OR Plane
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PAL Device Design Example
IO1
IO1
B
B
A
A
D
D
C
C
IO1
Not programmed
A
IO2
B
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CPLD and FPGA BrownRose 96

• Complex Programmable Logic Device (CPLD)
• Multiple PLDs (e.g. PALs, PLAs) with programmable
  interconnection structure
• Pioneered by Altera
• Field-Programmable Gate Array (FPGA)
• High logic capacity with large distributed
  interconnection structure
• Logic capacity ? number of 2-input NAND gates
• Offers more narrow logic resources
• CPLD offers logic resources w/ a wide number of
  inputs (AND planes)
• Offer a higher ratio of Flip-flops to logic
  resources than CPLD
• HCPLD (High Capacity PLD) is often used to refer
  to both CPLD and FPGA

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CPLD structure
Logic block
PLD
PLD
PLD
PLD
I/O block
PLD
PLD
PLD
PLD
Interconnects
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FPGA Structure
Logic block
I/O block
Interconnects
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FPGA Programmability

• Floating gate transistor
• Used in EPROM and EEPROM
• SRAM-controlled switch ? Control
• Pass transistors
• Multiplexers (to determine how to route inputs)
• Antifuse
• Similar to fuse
• Originally an Open-Circuit
• One-Time Programmable (OTP)