USB FX2 - PowerPoint PPT Presentation

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USB FX2

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USB interface to FPGA. FPGA for camera control and transfers. Sensor FPGA Memory ... Transfers from/to FIFO and USB is automatic and managed by hardware ... – PowerPoint PPT presentation

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Tags: usb | fx2 | usb

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Title: USB FX2


1
USB FX2
  • USB 2.0 devices
  • Cypress FX2 µC
  • 8051 core

2
Small camera interface laboratory project
  • USB interface to FPGA
  • FPGA for camera control and transfers
  • Sensor ? FPGA ? Memory
  • Memory ? FPGA ? USB FIFO (FX2)
  • FX2 ? PC

PC
CMOS sensor
FX2
FPGA
Memory
3
Data Flow
10 Mpixels/s 8 bits/clk
5 MDoublets/s 16 bits/transfer
PC
CMOS sensor
FX2
FPGA
Memory
2 2.5 MWords/s 32 bits/transfer
480 Mbits/s 1bit serial
4
FPGA architecture
NIOSII
JTAG UART
Camera Ctrl
FX2 interface
EPCS Ctrl
Avalon
SRAM
SDRAM Ctrl

i2c
5
Camera Controller architecture
Data
32 bits
Camera Interface
Avalon Master
4 pixels/transfer
HSync
NewData
DataAck
VSync
NewFrame
MClk
Stop
Mode
Start
Avalon Slave
Start Address
Length
Start
Avalon
6
FPGA4U general schematics
7
USB 2 interface
  • Interface between FPGA and USB
  • µC FX2
  • Transfer through FIFO
  • Control by RD/WR signals

FPGA
8
FX2 General View (128 pins)
9
FX2 general architecture
10
FX2 3 packages interfaces
Basic system GPIF/FIFO mode
Extension GPIF, Serial, Timer
External Address/Data bus
11
FX2 endpoints variations
12
FIFO interface (Slave Mode)
  • A slave FIFO interface allows direct access to
    the endpoints by an external master
  • FIFO Rd
  • FIFO Wr
  • 16 bits data bus
  • Handshake control signals

13
FIFO interface (Slave Mode)
14
FIFO interface (Slave Mode)
  • Polarity programmable (Active High or Low)
  • SLCS Select the FX2 FIFO
  • SLRD Read next data
  • SLWR Write provided data
  • SLOE Data Output Enable
  • FIFOAdR1..0 Select FIFO (endpoint) to use

15
FIFO interface (Slave Mode)
  • Polarity programmable (Active High or Low)
  • FLAG A, B(Full), C(Empty)
  • Programmable Output Function for FIFO
  • PKTEND Allow signalization of an end of packet
  • A not full Packet can be send
  • Synchronous or Asynchronous transfers control
  • Data Bus 8/16 bits wide
  • Allow until 96 Mbytes of data transfers rate gtgt
    USB HS

16
FIFO interface (Slave Mode)
17
FIFO interface (Slave Mode)
18
GPIF General Programmable InterFace
  • A specific programmable state machine available
    for Master (FX2) fast transfers through FIFO
  • Transfers from/to FIFO and USB is automatic and
    managed by hardware
  • Programmable Control signals with external systems

19
FIFO GPIF Master Mode
20
FX2 GPIF architecture
21
IFClk
  • The IF Clk can be generated by the FX2 or be
    provided by the external interface
  • Programmable Polarity
  • 30/48MHz

22
IFCLK
23
IFCLK
  • On FPGA4U IFClk at 48MHz is coming to the FPGA
  • Allow synchronized synchronous transfers in FIFO
    mode
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