Challenges in the RF Design of highly integrated Direct Conversion Receivers for multiband multistan


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Challenges in the RF Design of highly integrated
Direct Conversion Receivers for multi-band
multi-standard applications
Francesco Svelto
Laboratorio di Microelettronica Università degli
Studi di Pavia Italy
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This Talk
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This Talk
A 0.13 mm CMOS Front-End for DCS1800/UMTS/802.11b-
g
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This Talk
An Interference Robust 0.18mm CMOS 3.1-8GHz UWB
Receiver Front-End
A Variable Gain RF Front-End for Multistandard
WLANs Applications
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A CMOS Direct Downconverter with 78dBm Minimum
IIP2 for 3G Cell-Phones
International Solid-State Circuits Conference
Feb. 2005
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State-of-the-Art Hybrid Zero-IF UMTS RX

• TX signal leakage sets challenging RX IIP2
  (gt50dBm)
• Expensive external SAW filter alleviates IIP2 and
  IIP3 specs

Goal fully integrated solution
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Mechanisms of 2nd Order Intermodulation
Counter-measures
RF-LO coupling Orthogonal RF and LO paths
Mismatch in load resistors Fully differential
V-I converter (IIP2CM 40dBm) and 0.1 load
resistors mismatch IIP2 gt 100dBm!
V-I converter AC coupling
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2nd Order Distortion in Switching Pairs

• Very high IIP2 (gt90dBm) at low frequency
• Dramatic drop at radio frequency

Parasitic capacitor at source nodes plays a key
role
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Switching Pair Equivalent Model
VS - Frequency
VS - Time
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IM2 Due to LO odd-harmonics
Tail current
Source voltage VS
IM2 sidebands
Capacitor current down-converted by device
commutation
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IM2 due to LO even-harmonics
Tail current
Source voltage VS
IM2 sidebands
Gain at even LO harmonics due to duty-cycle
distortion
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IM2 contributions from harmonics
W/L200/0.3 mm/mm I2mA
Power of down-converted side-bands around
fundamental at least 17dB higher
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Suppressing IM2 due to Switching Pairs

• LSW is chosen with same impedance magnitude as
  Cpar at LO frequency

• CFAT drains IM2 currents flowing through LSW

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IM2 contributions with LC filter
High order harmonics are almost unchanged
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V-I Converter

• AC Coupling tranconductor and switching pair is
  a solution
• but price is consumption
• Fully differential for high IIP2
  Pseudo-differential for high IIP3

RC degeneration leads to high IIP2 and high IIP3
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V-I Converter IIP2
Low gain at low frequency improves IIP2
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V-I Converter IIP3
Cdeg provides low impedance at signal frequency
high IIP3
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Downconverter Schematic

• Differential load resistors save voltage room
• Common-mode feedback sets DC output voltage
• 4mA from 1.8V supply

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Die Photo

• Differential inductor with central tap RF
  grounded by MIM capacitor
• Highly interdigitated devices for matching
• Orthogonal LO and RF paths where crossing
• 2.2mm2 die area(1.2mm2 active area)

STMicroelectronics 0.18mm RFCMOS - LQFP32 Package
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IIP2 Measurement

• The two tones are filtered by the mixer RC load

• Differential probe has negligible impact on
  measured IIP2

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IIP2 Statistics
78dBmminimum IIP2
Lot 1 March 2004 Lot 2 June 2005
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IIP2 Statistics without Cfat
IIP2 without Cfat
X
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Conversion Gain and Noise

• Conversion gain
• 16dB in-band gain
• 4.5MHz output bandwidth

• Input referred noise
• 350kHz 1/f noise corner
• 4nV/vHz average noise 10kHz-1.92MHz

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Measurement Summary
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Zero-IF UMTS Receiver

• Assuming
• 18dB LNA peak gain Q10 13dB gain at
  1.98GHz
• 0dBm LNA IIP3out-of-band
• Downconverter with measured performance

IIP2 gt 65dBm IIP3out-of-band -3dBm
Antenna input
Fully integrated zero-IF 3G receiver is feasible
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A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct
Conversion Front End for GSM in 90nm CMOS
International Solid-State Circuits Conference
Feb. 2006
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Wireless Receivers in Deep-Submicron CMOS
Extremely high dynamic range at low voltagein
cellular direct conversion solutions
90nm GSM Front-End at 750mV to be compatible
with 65nm and 45nm nodes
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Low-Voltage RX Front-End for GSM

• Few stacked devices

Requires high supply voltage
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Pseudo-Differential Input Stage
Suffers from excessive CM distortion IIP2CM
5dBm(W50mm I4mA)

• Mechanism 1
• IIM2CM transfers to the output still as a CM
  current
• DR conversion CM diff.

• Load resistors
• (DR/R0.3) sDR/R -50dB

Mixer IIP2 lt 55dBm Inadequate!
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Leakage Through the Commutating Pairs

• Mechanism 2
• Voff1 and Voff2 determine different leakage
  gainsIM2DIFF at mixer output

• Transconductor IIP2CM 5dBm
• Leakage (Voff 2mV) sL -50dB

Mixer IIP2 lt 55dBm Inadequate!
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Solution Shunt-Shunt Feedback

• Low-frequency CM feedback loop attenuates IIM2CM

• Transconductor IIP2CM 5dBm sDR/R sL
  -50dB1GLOOP gt 40dB

Mixer IIP2 gt 90dBm!
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PCS1900 Direct-Downconverter Schematic

• PCM injects common-mode noise No noise penalty

• PL reduces voltage drop on R1

• gmRF 24mS further reduces switches 1/f noise
  contribution trading IIP2 and IIP3

• 5mA from 750mV-VDD

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PCS1900 Low-Noise Amplifier Schematic

• Inductive degeneration for very low NF

• Partially external input impedance matching
  minimizes NF

• 5mA from 750mV-VDD

From simulations Gain 23dB NF 1.6dB
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Die Photo

• Dedicated RF ground avoids noise coupling from
  the substrate

• Highly interdigitated devices for matching

• 4.3mm2 die area(2.7mm2 active area)

• STMicroelectronics CMOS090 (90nm) - LQFP32
  Package

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Input Impedance Matching and RF Gain
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Noise Power Spectral Density
15kHz 1/f noise corner Average Noise Figure
1kHz-100kHz 3.5dB
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IIP2
51 dBm minimumover 25 samples
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Measurement Summary
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Injection Locked dividers for Quadrature
Generation in Direct Conversion CMOS Receivers
Journal of Solid-State Circuits Sept.
2004 Custom Integrated Circuits Conference Sept.
2003
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Local Oscillator Generation

• Low phase noise at large offset
• Large tuning range
• Minimum power consumption

while driving large mixer LO input capacitance
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Coupled LC Oscillators

• Quadrature accuracy trades with phase noise

• Fixed capacitances reduce the available tuning
  range

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Injection Locking Frequency Dividers
A VCO running at 2w0 drives two LC frequency
dividers

• Phase noise and tuning range set by the VCO
• Quadrature accuracy set by dividers
• Dividers must feature enough locking band

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Regenerative Model

• Harmonic components other
• than the fundamental are
• filtered-out by the LC tank
• For correct regeneration the
• loop phase shift is

a(j) b(w-w0) 0

• The DC current is actually limiting the locking
  range
• (es. if IDC Iinj amax 30)

j -b(w-w0) / 2
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Locking Range and Quadrature Accuracy
Locking-range and phase accuracy improve
reducing load Q and increasing injection ratio
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CMOS Direct Conversion front-end

• Fully Differential Topology
• DC offset cancellation loop
• 0.18mm CMOS Technology
• Double Frequency VCO
• Second-Harmonic Injection Locking Dividers

Servo-loop around the VGA implements a 3kHz high
pass filter
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Die Microphotograph
4.7mm
IQ VGA servo loop
IQ mixer and dividers
3.4mm
VCO
LNA
Total chip area 16mm2
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Double Frequency VCO
Improved tuning
Separate supply voltage Improved tuning
Range Improved PSRR
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Dividers Implementation
40/ 0.25

• Capacitive load parasitic only
• Q lowered to 4 to keep a safety margin on
  quadrature error
• Input trasconductor in subthresold for maximum
  Iinjection

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VCO Tuning Range
Lower oscillation frequency due to LC load
variation
10.6
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Locking range and Phase deviation
Locking Range
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measurements
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model
IINJ/IDC1.5
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IINJ/IDC0.5
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Phase Deviation
Phase Deviation (down-converted signals)
IINJ/IDC0.9
4
3
2
1
0
1.73
1.78
1.83
1.88
1.93
1.98
2.03
2.08
Output Frequency GHz
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Phase Noise
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Performance Summary
VGA 95
LNA 24
IQ DIV 19
VCO 95
IQ Mixer 38
Power consumption breakdown
Integrated between 200 kHz and 1.92 MHz
Integrated between 10 kHz and 1.92 MHz
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Injection Locked Balanced Dividers
Fully balanced multiplier suppress the DC current
42 measured locking range with Qtank 14
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Towards highly integrated Multiband
MultistandardReceivers
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Universal Mobile Terminals
Ultimate solution Zero-IF fully integrated
multistandard RX

• Mixer and analog base-band blocks are easily
  re-configurable
• LNA is the most critical block for multistandard
  operation

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LNA State-of-the-Art
Resonant network for voltage gain
Resonant network for input impedance matching
Two resonant networks must be reconfigured for
multistandard operation critical in the
GHz range
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Feedback Amplifier
Series-shunt feedback Input impedance
Voltage gain (input matched)

• Biasing current not set by impedance matching
  constraints allows optimization of NF and IIP3
• Load reconfiguration allows multi-standard
  operations

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Multi-Band Feedback LNA
Programmable resonance frequency load
f1
f2
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Concurrent Feedback LNA
Multiple resonant load
f1
f2
f3
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Positive Feedback based solution
Input Impedance
Current Gain

• gm1 gt 1/Rs
• Current gain greater than 1

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A 0.13 mm CMOS Front-End for DCS1800/UMTS/802.11b-
g with Multi-band Positive Feedback Low Noise
Amplifier
VLSI Symposium on Circuits June 2005
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Multi-Standard Scenario
Applications

• Cellular (DCS1800)
• Data (IEEE802.11b/g)
• Mixed voice/data (UMTS)

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Multi-Band LNA

• Positive feedback realized by M2-M4
• Re-configurable LC load by inductor selection

• Three selectable bands
• 6dB gain variation

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Multi-Standard Mixer Transconductor

• Different noise-linearity trade-off for each
  standard

• GSM requires higher gm than UMTS and WLAN but
  asks for lower IIP3

• Switch V1 sets the transconductance gain

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Multi-Standard Mixer Switching Pairs

• LC filter improves noise and linearity

• PMOS switching pairs for low 1/f noise

• Multi-mode RC load sets appropriate gain and
  bandwidth for each standard

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Input Matching
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Gain
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Performance summary
Current Consumption 20mA Voltage Supply 1.8V
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A Variable Gain RF Front-End Based on a Voltage
Voltage Feedback LNA for Multistandard
Applications
Journal of Solid-State Circuits March 2005
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5-6GHz Multi-Standard WLAN Scenario

• About 1GHz overall bandwidth
• Spectrum allocation fragmented in 100-250MHz
  sub-bands

Multi-standard narrow-band re-configurable
receiver
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WLAN Multi-Band LNA
Tunable LC load 8 selectable bands between
4.9-5.825GHz
Capacitive feedback
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Variable Gain Mixer

• Pseudo differential NMOS input stage
• Input stage current boosting
• Differential inductor (Lquad7nH)

• Variable gain feature
• 11dB gain reduction
• 3.5dB IIP3 improvement
• Constant output pole cut-off frequency and DC
  output level

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Die Photomicrograph
Bias

• Chip area 1.6mm2
• PackageQFN 36
• PAD ESD protected

Mixer Q
Mixer I
LNA
Technology STMicroelectronics (BiCMOS7G)
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Input Impedance Matching
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Front-End Gain
Fixed IF frequency (500kHz)
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Performance Summary
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An Interference Robust 0.18mm CMOS 3.1-8GHz
Receiver Front-End for UWB Radio
Custom Integrated Circuits Conference Sept. 2005
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Multi-Band OFDM UWB Scenario

• Group 1 mandatory groups 2 - 5 optional
• Huge 5-6GHz WLAN interferer can desensitize the
  UWB RX

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Multi-Resonance UWB LNA

• Feedback-based LNA for superior dynamic range
• 11dB simulated WLAN attenuation

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IQ Mixers
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Gain and Input Matching
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Performance summary
Current Consumption 10mA Voltage Supply 1.8V
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Acknowledgements
These works have been carried on by the following
phd students Francesco Gatta Danilo
Manstretta Paolo Rossi Massimo Brandolini
Antonio Liscidini Andrea Mazzanti Paola
Uggetti Giuseppe Cusmai Marco Sosio. I am
indebted with them.