HCAL Data Concentrator Status Report

1
HCAL Data ConcentratorStatus Report

• Gueorgui Antchev, Eric Hazen, Jim Rohlf,
  Shouxiang Wu
• Boston University

2
DCC Engineering Status

• Two prototype boards working
• Successful transfer of simulatedHTR data to VME
  spy buffer at full PCI speeds
• Simple event builder working FPGA coding for
  more advanced version underway

3
DCC Demonstrator
Working since Fall Used for Source
Test Development Finished
Data Concentrator Logic PMC
PCI Interfaces Not working Due to layout Error
TTCRx
PCI
Universe
33/32
DCC
PCI
PCI-VME
FPGA
Bridge
33/64
SDRAM
to CPU
S-Link (64) LSC
PCI
33/32
One 3-channel receiver On PMC Adapter
4
DCC Demonstrator
LVDS Serial Link Receiver
TTCRx
S-Link LSC (Transmitter)
DCC Logic Board
Spare PMC Sitefor Testing
5
DCC Prototype
PC-MIP Mezzanine Cards
3 Channel Link Receivers
Data Concentrator Logic PMC
Overflow Warning Fast Busy To TTS
TTCRx
PCI
Universe
33/32
DCC
PCI-VME
PCI
FPGA
Bridge
33/64
Data from HTR Modules
SDRAM
to RUI
S-Link (64) LSC
PCI
33/32
6
DCC Final Configuration
9Ux400 VME Motherboard (Design Frozen)
DCC Logic Mezzanine Card
TTCRx
Proposed Transition Module
3x Link Receiver
VME
DAQ S-LINK
FE Data from HTR Cards (LVDS Serial)
Trigger S-LINK
Spare Standard PMC Site (33MHz 64 bit)
Fast Timing/ Control
235 pin 2mm Connector
FPGA
7
DCC Logic Board
8
DCC Xilinx Chip
8MB DDR SDRAM
Write PORT
XILINX -XC2V1000
Port 3 Write
DDR SDRAM control
32
Address/Contr.
JTAG
DAQ FIFO Write
32bit/128MHz
Read PORT
32
DAQ FIFO Read
EVENT BUILDER
Port 3 Read
Arbiter
DAQ FIFO Read
Main S-LINK Port
DAQ S-LINK
32bit/128MHz
DAQ FIFO Read 4KB
TTCF out
TTCrx FIFO 4KB
TTCrx Contr.
TTCrx board
32bit/33MHz
64bit/128MHz
Complete?
32bit/66MHz
32bit
32bit/128MHz
Port 3
DAQ FIFO Write 4KB
Preliminary ?
DAQ FIFO Write
To be done
PCI1 ACEX
XILINX Config.
Port1
Port1 FIFO 4KB
Port 3 Write
Port 3 FIFO Write 16words
1Mx8 FLASH
64bit/128MHz
16bit/66MHz
Port 3 FIFO Read 16words
36bit/128MHz
32bit/33MHz
Port 3 Read
PCI2 ACEX
PCI3 ACEX
Port2
Port2 FIFO 4KB
SPY FIFO 8KB
16bit/66MHz
Monitor FIFO 4KB
32bit/33MHz
32bit/33MHz
32bit/128MHz
Trig FIFO 32KB
Trig S-LINK Port
Trig S-LINK
LVDS Fast Monitoring
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DCC Logic Status

• Complete data path working
• PCI 1/2 masters working
• Event builder
• Preliminary version which just glues together HTR
  data as-is to form events
• DDR SDRAM (1Gbyte/sec) interface
• Dual-port logic for DAQ FIFO and VME Spy FIFO
• Working identical logic in use on D0 STT
• Simple VME interface for control/spy

10
DCC Prototype Plans

• Short-term goal bandwidth test
• Currently 9 clocks PCI overhead per eventFor 100
  byte events (typical) we get 240 Mbytes/s
• Further testing/optimization underway
• Finish event builder
• Need to settle HTR?DCC and DCC?FED formats
• Implement monitoring
• What do we need to monitor? Lots of FPGA gates
  available
• Implement trigger S-Link output
• Test TTCRx input
• Integrate with HTR Prototype
• Use for test beam

11
DCC Production Design

• One more logic board prototype
• Transition module for two S-Links
• TTC Fanout input
• Final fast monitoring/status outputs
• Overall Status
• Motherboard and Link Receiver design done
• Production purchase soon (this year!) 50k each
• Logic board design could in principle be done by
  this summer, but would like to delay production
  as long as possible (from an engineering
  standpoint)
• Production cost also 50k
• S-Link Transition module is NEW HARDWARE
• No formal cost estimate, but should easily be
  funded by cost savings in remainder of DCC

12
Lehman 2001 Schedule
new estimate
Are we in trouble? Maybe