Variables, Attributes, Functions and Procedures, Data Types

1
Variables, Attributes, Functions and
Procedures,Data Types
ECE 545 Lecture 10
2
Resources

• Volnei A. Pedroni, Circuit Design with VHDL
• Chapter 7, Signals and Variables
• Chapter 11, Functions and Procedures
• Sundar Rajan, Essential VHDL RTL Synthesis
• Done Right
• Chapter 11, Scalable and Parameterizable
• Design
• Chapter 12, Enhancing Design Readability
• and Reuse

3
Combinational Logic Synthesis for Intermediates
4
2-to-4 Decoder
y
w
w
y
y
y
En
0
1
0
1
2
3
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
1
1
0
0
0
1
x
x
0
0
0
0
0
(a) Truth table
(b) Graphical symbol
5
VHDL code for a 2-to-4 Decoder
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY dec2to4 IS PORT ( w IN
STD_LOGIC_VECTOR(1 DOWNTO 0) En IN
STD_LOGIC y OUT STD_LOGIC_VECTOR(3
DOWNTO 0) ) END dec2to4 ARCHITECTURE
dataflow OF dec2to4 IS SIGNAL Enw
STD_LOGIC_VECTOR(2 DOWNTO 0) BEGIN Enw lt En
w WITH Enw SELECT y lt 0001" WHEN
"100", "0010" WHEN "101", "0100" WHEN
"110", 1000" WHEN "111", "0000" WHEN
OTHERS END dataflow
6
Describing combinational logic using processes
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY dec2to4 IS PORT ( w IN
STD_LOGIC_VECTOR(1 DOWNTO 0) En IN
STD_LOGIC y OUT STD_LOGIC_VECTOR(0 TO 3)
) END dec2to4 ARCHITECTURE Behavior OF
dec2to4 IS BEGIN PROCESS ( w, En ) BEGIN IF
En '1' THEN CASE w IS WHEN "00" gt y lt
"1000" WHEN "01" gt y lt "0100" WHEN
"10" gt y lt "0010" WHEN OTHERS gt y lt
"0001" END CASE ELSE y lt "0000"
END IF END PROCESS END Behavior
7
Describing combinational logic using processes
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY seg7 IS PORT ( bcd IN
STD_LOGIC_VECTOR(3 DOWNTO 0) leds OUT
STD_LOGIC_VECTOR(1 TO 7) ) END seg7
ARCHITECTURE Behavior OF seg7
IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS
-- abcdefg WHEN "0000" gt leds lt
"1111110" WHEN "0001" gt leds lt
"0110000" WHEN "0010" gt leds lt
"1101101" WHEN "0011" gt leds lt
"1111001" WHEN "0100" gt leds lt
"0110011" WHEN "0101" gt leds lt
"1011011" WHEN "0110" gt leds lt
"1011111" WHEN "0111" gt leds lt
"1110000" WHEN "1000" gt leds lt
"1111111" WHEN "1001" gt leds lt
"1110011" WHEN OTHERS gt leds lt
"-------" END CASE END PROCESS END
Behavior
8
Describing combinational logic using processes
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY compare1 IS PORT ( A, B IN
STD_LOGIC AeqB OUT STD_LOGIC ) END
compare1 ARCHITECTURE Behavior OF compare1
IS BEGIN PROCESS ( A, B ) BEGIN AeqB lt '0'
IF A B THEN AeqB lt '1' END IF
END PROCESS END Behavior
9
Incorrect code for combinational logic- Implied
latch (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY implied IS PORT ( A, B IN
STD_LOGIC AeqB OUT STD_LOGIC ) END
implied ARCHITECTURE Behavior OF implied
IS BEGIN PROCESS ( A, B ) BEGIN IF A B
THEN AeqB lt '1' END IF END PROCESS
END Behavior
10
Incorrect code for combinational logic- Implied
latch (2)
11
Describing combinational logic using processes
Rules that need to be followed

• All inputs to the combinational circuit should be
  included
• in the sensitivity list
• No other signals should be included
• in the sensitivity list
• None of the statements within the process
• should be sensitive to rising or falling edges
• All possible cases need to be covered in the
  internal
• IF and CASE statements in order to avoid
• implied latches

12
Covering all cases in the IF statement
Using ELSE
IF A B THEN AeqB lt '1'
ELSE AeqB lt '0'
Using default values
AeqB lt '0' IF A B THEN AeqB lt '1'
13
Covering all cases in the CASE statement
Using WHEN OTHERS
CASE y IS WHEN S1 gt Z lt "10"
WHEN S2 gt Z lt "01" WHEN S3 gt Z lt
"00" WHEN OTHERS gt Z lt --" END
CASE
CASE y IS WHEN S1 gt Z lt "10"
WHEN S2 gt Z lt "01" WHEN OTHERS gt Z lt
"00" END CASE
Using default values
Z lt "00" CASE y IS WHEN S1 gt Z lt
"10" WHEN S2 gt Z lt "10" END CASE
14
Combinational Logic Synthesis for Advanced
15
Advanced VHDL for synthesis

• For complex, generic, and/or regular circuits
• you may consider using
• PROCESSES with internal
• VARIABLES and
• FOR LOOPs

16
Variables
17
Variable Example (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY Numbits IS
• PORT ( X IN STD_LOGIC_VECTOR(1 TO 3)
• Count OUT INTEGER RANGE 0 TO 3)
• END Numbits

18
Variable Example (2)

• ARCHITECTURE Behavior OF Numbits IS
• BEGIN
• PROCESS(X) count the number of bits in X equal
  to 1
• VARIABLE Tmp INTEGER
• BEGIN
• Tmp 0
• FOR i IN 1 TO 3 LOOP
• IF X(i) 1 THEN
• Tmp Tmp 1
• END IF
• END LOOP
• Count lt Tmp
• END PROCESS
• END Behavior

19
Variables - features

• Can only be declared within processes and
  subprograms (functions procedures)
• Initial value can be explicitly specified in the
  declaration
• When assigned take an assigned value immediately
• Variable assignments represent the desired
  behavior, not the structure of the circuit
• Should be avoided, or at least used with caution
  in a synthesizable code

20
Variables vs. Signals
21
Variable Example

• ARCHITECTURE Behavior OF Numbits IS
• BEGIN
• PROCESS(X) count the number of bits in X equal
  to 1
• VARIABLE Tmp INTEGER
• BEGIN
• Tmp 0
• FOR i IN 1 TO 3 LOOP
• IF X(i) 1 THEN
• Tmp Tmp 1
• END IF
• END LOOP
• Count lt Tmp
• END PROCESS
• END Behavior

22
Incorrect Code using Signals

• ARCHITECTURE Behavior OF Numbits IS
• SIGNAL Tmp INTEGER RANGE 0 TO 3
• BEGIN
• PROCESS(X) count the number of bits in X equal
  to 1
• BEGIN
• Tmp lt 0
• FOR i IN 1 TO 3 LOOP
• IF X(i) 1 THEN
• Tmp lt Tmp 1
• END IF
• END LOOP
• Count lt Tmp
• END PROCESS
• END Behavior

23
N-bit NAND

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY NANDn IS
• GENERIC (n INTEGER 8)
• PORT ( X IN STD_LOGIC_VECTOR(1 TO n)
• Y OUT STD_LOGIC)
• END NANDn

24
N-bit NAND architecture using variables

• ARCHITECTURE behavioral1 OF NANDn IS
• BEGIN
• PROCESS (X)
• VARIABLE Tmp STD_LOGIC
• BEGIN
• Tmp X(1)
• AND_bits FOR i IN 2 TO n LOOP
• Tmp Tmp AND X( i )
• END LOOP AND_bits
• Y lt NOT Tmp
• END PROCESS
• END behavioral1

25
Incorrect N-bit NAND architecture using signals

• ARCHITECTURE behavioral2 OF NANDn IS
• SIGNAL Tmp STD_LOGIC
• BEGIN
• PROCESS (X)
• BEGIN
• Tmp lt X(1)
• AND_bits FOR i IN 2 TO n LOOP
• Tmp lt Tmp AND X( i )
• END LOOP AND_bits
• Y lt NOT Tmp
• END PROCESS
• END behavioral2

26
Correct N-bit NAND architecture using signals

• ARCHITECTURE dataflow1 OF NANDn IS
• SIGNAL Tmp STD_LOGIC_VECTOR(1 TO n)
• BEGIN
• Tmp(1) lt X(1)
• AND_bits FOR i IN 2 TO n GENERATE
• Tmp(i) lt Tmp(i-1) AND X( i )
• END LOOP AND_bits
• Y lt NOT Tmp(n)
• END dataflow1

27
Correct N-bit NAND architecture using signals

• ARCHITECTURE dataflow2 OF NANDn IS
• SIGNAL Tmp STD_LOGIC_VECTOR(1 TO n)
• BEGIN
• Tmp lt (OTHERS gt 1)
• Y lt 0 WHEN X Tmp ELSE 1
• END dataflow2

28
Parity generator entity

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY oddParityLoop IS
• GENERIC ( width INTEGER 8 )
• PORT ( ad in STD_LOGIC_VECTOR (width - 1
  DOWNTO 0)
• oddParity out STD_LOGIC )
• END oddParityLoop

29
Parity generator architecture using signals

• ARCHITECTURE dataflow OF oddParityGen IS
• SIGNAL genXor STD_LOGIC_VECTOR(width DOWNTO 0)
• BEGIN
• genXor(0) lt '0'
• parTree FOR i IN 1 TO width GENERATE
• genXor(i) lt genXor(i - 1) XOR ad(i - 1)
• END GENERATE
• oddParity lt genXor(width)
• END dataflow

30
Parity generator architecture using variables

• ARCHITECTURE behavioral OF oddParityLoop IS
• BEGIN
• PROCESS (ad)
• VARIABLE loopXor STD_LOGIC
• BEGIN
• loopXor '0'
• FOR i IN 0 to width -1 LOOP
• loopXor loopXor XOR ad( i )
• END LOOP
• oddParity lt loopXor
• END PROCESS
• END behavioral

31
Sequential Logic Synthesis for Beginners
32
For Beginners

• Use processes with very simple structure only
• to describe
• - registers
• - shift registers
• - counters
• - state machines.
• Use examples discussed in class as a template.
• Create generic entities for registers, shift
  registers, and
• counters, and instantiate the corresponding
  components in
• a higher level circuit using GENERIC MAP PORT
  MAP.
• Supplement sequential components with
• combinational logic described using concurrent
  statements.

33
Sequential Logic Synthesis for Intermediates
34
For Intermmediates

• Use Processes with IF and CASE statements only.
  Do not use LOOPS or VARIABLES.
• Sensitivity list of the PROCESS should include
  only signals that can by themsleves change the
  outputs of the sequential circuit (typically,
  clock and asynchronous set or reset)
• Do not use PROCESSes without sensitivity list
• (they can be synthesizable, but make simulation
  inefficient)

35
Constrained Array Types
36
One-dimensional arrays Examples (1)

• type word_asc is array(0 to 31) of std_logic
• type word_desc is array(31 downto 0) of
  std_logic
• ..
• signal buffer_register word_desc
• ..
• buffer_register(6) lt 1
• ..
• variable tmp word_asc
• ..
• tmp(5) 0

37
One-dimensional arrays Examples (2)

• type controller_state is (initial, idle, active,
  error)
• type state_counts_imp is array(idle to error) of
  natural
• type state_counts_exp is array(controller_state
  range idle to error) of natural
• type state_counts_full is array(controller_state)
  of natural
• ..
• variable counters state_counts_exp
• ..
• counters(active) 0
• ..
• counters(active) counters(active) 1

38
Unconstrained Array Types
39
Predefined Unconstrained Array Types

• Predefined
• bit_vector array of bits
• string array of characters
• Defined in the ieee.std_logic_1164 package
• std_logic_vector array of std_logic_vectors

40
Predefined Unconstrained Array Types

• subtype byte is bit_vector(7 downto 0)
• .
• variable channel_busy bit_vector(1 to 4)
• .
• constant ready_message string ready
• .
• signal memory_bus std_logic_vector (31 downto 0)

41
User-defined Unconstrained Array Types

• type sample is array (natural range ltgt) of
  integer
• .
• variable long_sample is sample(0 to 255)
• .
• constant look_up_table_1 sample
• (127, -45, 63, 23, 76)
• .

42
Attributes of Arrays and Array Types
43
Array Attributes

• Aleft(N) left bound of index range of dimension
  N of A
• Aright(N) right bound of index range of
  dimension N of A
• Alow(N) lower bound of index range of dimension
  N of A
• Ahigh(N) upper bound of index range of dimension
  N of A
• Arange(N) index range of dimension N of A
• Areverse_range(N) reversed index range of
  dimension N of A
• Alength(N) length of index range of dimension N
  of A
• Aascending(N) true if index range of dimension
  N of A
• is an ascending range,
  false otherwise

44
Array Attributes - Examples

• type A is array (1 to 4, 31 downto 0)
• Aleft(1) 1
• Aright(2) 0
• Alow(1) 1
• Ahigh(2) 31
• Arange(1) 1 to 4
• Alength(2) 32
• Aascending(2) false

45
Subprograms
46
Subprograms

• Include
• functions and procedures
• Commonly used pieces of code
• Can be placed in a library, and then reused and
  shared among various projects
• Abstract operations that are repeatedly performed
• Type conversions
• Use only sequential statements, the same as
  processes

47
Typical locations of subprograms
PACKAGE PACKAGE BODY
LIBRARY
global
ENTITY
FUNCTION / PROCEDURE
local for all architectures of a given entity
ARCHITECTURE Declarative part
local for a given architecture
48
Functions
49
Functions basic features

• Functions
• always return a single value as a result
• Are called using formal and actual parameters the
  same way as components
• never modify parameters passed to them
• parameters can only be constants (including
  generics) and signals (including ports)
• variables are not allowed the default is a
  CONSTANT
• when passing parameters, no range specification
  should be included (for example no RANGE for
  INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)
• are always used in some expression, and not
  called on their own

50
Function syntax

• FUNCTION function_name (ltparameter_listgt)
• RETURN data_type IS
• declarations
• BEGIN
• (sequential statements)
• END function_name

51
Function parameters - example

• FUNCTION f1
• (a, b INTEGER SIGNAL c STD_LOGIC_VECTOR)
• RETURN BOOLEAN IS
• BEGIN
• (sequantial statements)
• END f1

52
Function calls - examples

• x lt conv_integer(a)
• IF x gt maximum(a, b) THEN ....
• WHILE minimum(a, b) LOOP
• .......

53
Function Example 1

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE my_package IS
• FUNCTION log2_ceil (CONSTANT s INTEGER) RETURN
  INTEGER
• END my_package
• PACKAGE body my_package IS
• FUNCTION log2_ceil (CONSTANT s INTEGER)
  RETURN INTEGER IS
• VARIABLE m,n INTEGER
• BEGIN
• m 0
• n 1
• WHILE (n lt s) LOOP
• m m 1
• n n2
• END LOOP
• RETURN m
• END log2_ceil

54
Function call Example 1

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE ieee.std_logic_unsigned.all
• USE work.my_package.all
• ENTITY log2_int IS
• GENERIC (m INTEGER 20)
• PORT (x IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• y OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
• )
• END log2_int
• ARCHITECTURE log2_int OF log2_int IS
• CONSTANT l2m INTEGER log2_ceil (m)
• SIGNAL r STD_LOGIC_VECTOR(3 DOWNTO
  0)
• BEGIN
• r lt conv_std_logic_vector(l2m,4)
• y lt xr
• END log2_int

55
Function Example 2

• library IEEE
• use IEEE.std_logic_1164.all
• ENTITY powerOfFour IS
• PORT(
• X IN INTEGER
• Y OUT INTEGER
• )
• END powerOfFour

56
Function Example 2

• ARCHITECTURE behavioral OF powerOfFour IS
• FUNCTION Pow ( SIGNAL NINTEGER Exp
  INTEGER) RETURN INTEGER IS
• VARIABLE Result INTEGER 1
• BEGIN
• FOR i IN 1 TO Exp LOOP
• Result Result N
• END LOOP
• RETURN( Result )
• END Pow
• BEGIN
• Y lt Pow(X, 4)
• END behavioral

57
Package containing a function (1)

• LIBRARY IEEE
• USE IEEE.std_logic_1164.all
• PACKAGE specialFunctions IS
• FUNCTION Pow( SIGNAL N INTEGER Exp
  INTEGER) RETURN INTEGER
• END specialFunctions

58
Package containing a function (2)

• PACKAGE BODY specialFunctions IS
• FUNCTION Pow(SIGNAL N INTEGER Exp INTEGER)
• RETURN INTEGER IS
• VARIABLE Result INTEGER 1
• BEGIN
• FOR i IN 1 TO Exp LOOP
• Result Result N
• END LOOP
• RETURN( Result )
• END Pow
• END specialFunctions

59
Type conversion function (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• --------------------------------------------------
  -----------------------------------------------
• PACKAGE my_package IS
• FUNCTION conv_integer (SIGNAL vector
  STD_LOGIC_VECTOR)
• RETURN INTEGER
• END my_package
• --------------------------------------------------
  -----------------------------------------------

60
Type conversion function (2)

• PACKAGE BODY my_package IS
• FUNCTION conv_integer (SIGNAL vector
  STD_LOGIC_VECTOR)
• RETURN INTEGER
• VARIABLE result INTEGER RANGE 0 TO
  2vectorLENGTH - 1
• VARIABLE carry STD_LOGIC
• BEGIN
• IF(vector(vectorHIGH)1 THEN result1
• ELSE result 0
• FOR i IN (vectorHIGH-1) DOWNTO
  (vectorLOW) LOOP
• result result2
• IF (vector(i) 1) THEN result
  result1
• END IF
• RETURN result
• END conv_integer
• END my_package

61
Type conversion function (3)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.my_package.all
• --------------------------------------------------
  -----------------------------------------------
• ENTITY conv_int2 IS
• PORT ( a IN STD_LOGIC_VECTOR (3 DOWNTO 0)
• y OUT INTEGER RANGE 0 TO 15)
• END conv_int2
• --------------------------------------------------
  -----------------------------------------------
• ARCHITECTURE my_arch OF conv_int2 IS
• BEGIN
• y lt conv_integer(a)
• END my_arch

62
Procedures
63
Procedures basic features

• Procedures
• do not return a value
• are called using formal and actual parameters the
  same way as components
• may modify parameters passed to them
• each parameter must have a mode IN, OUT, INOUT
• parameters can be constants (including generics),
  signals (including ports), and variablesthe
  default for inputs (mode in) is a constant, the
  default for outputs (modes out and inout) is a
  variable
• when passing parameters, range specification
  should be included (for example RANGE for
  INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR)
• Procedure calls are statements on their own

64
Procedure syntax

• PROCEDURE procedure_name (ltparameter_listgt) IS
• declarations
• BEGIN
• (sequential statements)
• END function_name

65
Procedure parameters - example

• FUNCTION f1
• (a, b INTEGER SIGNAL c STD_LOGIC_VECTOR)
• RETURN BOOLEAN IS
• BEGIN
• (sequantial statements)
• END f1

66
Procedure calls - examples

• compute_min_max(in1, in2, in3, out1, out2)
• divide(dividend, divisor, quotient, remainder)
• IF (a gt b) THEN
• compute_min_max(in1, in2, in3, out1, out2)
• .......

67
Procedure example (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.decProcs.all
• ENTITY decoder IS port (
• decIn IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• decOut OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
• )
• END decoder

68
Procedure example (2)

• ARCHITECTURE simple OF decoder IS
• PROCEDURE DEC2x4 (inputs in STD_LOGIC_VECTOR(1
  downto 0)
• decode out
  STD_LOGIC_VECTOR(3 downto 0)
• ) IS
• BEGIN
• CASE inputs IS
• WHEN "11" gt
• decode "1000"
• WHEN "10" gt
• decode "0100"
• WHEN "01" gt
• decode "0010"
• WHEN "00" gt
• decode "0001"
• WHEN others gt
• decode "0001"
• END case
• END DEC2x4

69
Operators
70
Operator as a function (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.al
• --------------------------------------------------
  -----------------------------------------------
• PACKAGE my_package IS
• FUNCTION "" (a, b STD_LOGIC_VECTOR)
• RETURN STD_LOGIC_VECTOR
• END my_package
• --------------------------------------------------
  -----------------------------------------------

71
Operator as a function (2)

• PACKAGE BODY my_package IS
• FUNCTION "" (a, b STD_LOGIC_VECTOR)
• RETURN STD_LOGIC_VECTOR
• VARIABLE result STD_LOGIC_VECTOR
• VARIABLE carry STD_LOGIC
• BEGIN
• carry 0
• FOR i IN aREVERSE_RANGE LOOP
• result(i) a(i) XOR b(i) XOR carry
• carry (a(i) AND b(i)) OR (a(i) AND
  carry) OR (b(i) AND carry))
• END LOOP
• RETURN result
• END ""
• END my_package

72
Operator Overloading
73
Operator overloading

• Operator overloading allows different argument
  types for a given operation (function)
• The VHDL tools resolve which of these functions
  to select based on the types of the inputs
• This selection is transparent to the user as long
  as the function has been defined for the given
  argument types.

74
Different declarations for the same operator -
Example

• Declarations in the package ieee.std_logic_unsigne
  d
• function ( L std_logic_vector
  Rstd_logic_vector) return std_logic_vector
• function ( L std_logic_vector R
  integer) return std_logic_vector
• function ( L std_logic_vector
  Rstd_logic) return std_logic_vector

75
Different declarations for the same operator -
Example

• signal count std_logic_vector(7 downto 0)
• You can use
• count lt count 0000_0001
• or
• count lt count 1
• or
• count lt count 1

76
VHDL as a Strongly Typed Language
77
Notion of type

• Type defines a set of values and a set of
  applicable operations
• Declaration of a type determines which values can
  be stored in an object (signal, variable,
  constant) of a given type
• Every object can only assume values of its
  nominated type
• Each operation (e.g., and, , ) includes the
  types of values to which the operation may be
  applied, and the type of the result
• The goal of strong typing is a detection of
  errors at an early stage of the design process

78
Example of strong typing

• architecture incorrect of example1 is
• type apples is range 0 to 100
• type oranges is range 0 to 100
• signal apple1 apples
• signal orange1 oranges
• begin
• apple1 lt orange1
• end incorrect

79
Type Classification
80
Classification of data types
81
Integer Types
82
Integer type

• Name integer
• Status predefined
• Contents all integer numbers representable
  on a particular host computer, but at
  least numbers in the range
• (231-1) .. 231-1

83
User defined integer types - Examples

• type day_of_month is range 0 to 31
• type year is range 0 to 2100
• type set_index_range is range 999 downto 100
• constant number_of_bits integer 32
• type bit_index is range 0 to number_of_bits-1

Values of bounds can be expressions, but need to
be known when the model is analyzed.
84
Enumeration Types
85
Predefined enumeration types (1)

• boolean (true, false)
• bit (0, 1)
• character VHDL-87
• 128 7-bit ASCII characters
• VHDL-93
• 256 ISO 8859 Latin-1 8-bit characters

86
Predefined enumeration types (2)

• severity_level (note, warning, error, failure)
• Predefined in VHDL-93 only
• file_open_kind
• (read_mode, write_mode, append_mode)
• file_open_status
• (open_ok, status_error, name_error,
  mode_error)

87
User-defined enumeration types - Examples

• type state is (S0, S1)
• type alu_function is (disable, pass, add,
  subtract,
• multiply, divide)
• type octal_digit is (0, 1, 2, 3, 4,
  5, 6, 7)
• type mixed is (lf, cr, ht, -, /, \)

Each value in an enumeration type must be
either an identifier or a character literal
88
Floating-Point Types
89
Floating point types

• Used to represent real numbers
• Numbers are represented using a significand
  (mantissa) part and an exponent part
• Conform to the IEEE standard 754 or 854
• Minimum size of representation that must be
• supported by the implementation of the VHDL
• standard
• VHDL-2001 64-bit representation
• VHDL-87, VHDL-93 32-bit representation

90
Real literals - examples

• 23.1 23.1
• 46E5 46 ? 105
• 1E12 1 ? 1012
• 1.234E09 1.234 ? 109
• 34.0e-08 34.0 ? 10-8
• 20.101E5 0.1012 ? 25 (2-12-3) ? 25
• 80.4E-6 0.48 ? 8-6 (4 ? 8-1) ? 8-6
• 160.a5E-8 0.a516 ? 16-8 (10?16-15?16-2) ?
  16-8

91
The ANSI/IEEE standard floating-point number
representation formats
92
User-defined floating-point types - Examples

• type input_level is range -10.0 to 10.0
• type probability is range 0.0 to 1.0
• constant max_output real 1.0E6
• constant min_output real 1.0E-6
• type output_range is max_output downto min_output

93
Attributes of Scalar Types
94
Attributes of all scalar types

• Tleft first (leftmost) value in T
• Tright last (rightmost) value in T
• Tlow least value in T
• Thigh greatest value in T
• Not available in VHDL-87
• Tascending
• true if T is an ascending range, false
  otherwise
• Timage(x) a string representing the value of x
• Tvalue(s) the value in T that is represented by s

95
Attributes of all scalar types - examples

• type index_range is range 21 downto 11
• index_rangeleft 21
• index_rangeright 11
• index_rangelow 11
• index_rangehigh 21
• index_rangeascending false
• index_rangeimage(14) 14
• index_rangevalue(20) 20

96
Attributes of discrete types

• Tpos(x) position number of x in T
• Tval(n) value in T at position n
• Tsucc(x) value in T at position one greater
  than position of x
• Tpred(x) value in T at position one less
  than position of x
• Tleftof(x) value in T at position one to the
  left of x
• Trightof(x) value in T at position one to the
  right of x

97
Attributes of discrete types - examples

• type logic_level is (unknown, low, undriven,
  high)
• logic_levelpos(unknown) 0
• logic_levelval(3) high
• logic_levelsucc(unknown) low
• logic_levelpred(undriven) low
• logic_levelleftof(unknown) error
• logic_levelrightof(undriven) high

98
Subtypes
99
Subtype

• Defines a subset of a base type values
• A condition that is used to determine which
  values are included in the subtype is called a
  constraint
• All operations that are applicable to the base
  type also apply to any of its subtypes
• Base type and subtype can be mixed in the
  operations, but the result must belong to the
  subtype, otherwise an error is generated.

100
Predefined subtypes

• natural integers ? 0
• positive integers gt 0
• Not predefined in VHDL-87
• delay_length time ? 0

101
User-defined subtypes - Examples

• subtype bit_index is integer range 31 downto 0
• subtype input_range is real range 1.0E-9 to
  1.0E12

102
Operators
103
Operators (1)
104
Operators (2)
105
Operators (3)