Power.org Technical Track for Power Architecture? Conference Series

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Power.org Technical Trackfor Power Architecture?
Conference Series

• Dr. Syed Ijlal Ali Shah

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Power.orgs mission and objectives

• Technology Objectives
• Enhance the Power ISA?
• Enhance the development infrastructure for Power
  Architecture processors in embedded and consumer
  applications
• Improve SoC design methodology and enablement
  around Power Architecture and IP cores

• Our mission
• Develop, enable and promote Power Architecture
  technology as the preferred open standard
  hardware development platform for the electronics
  industry

• Marketing Objectives
• Increase awareness of the Power brand in the
  electronics marketplace
• Demonstrate member value in collaborative
  marketing and brand management by proving cost
  efficiencies an economy of scale
• Promote the Power.org open model for
  collaborative development

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Power.orgs evolution and expansion
Market technology acceleration 2009 onward
Communal asset creation 2007-2008

• Expand membership base to accelerate technical
  work, market growth
• Enhance programs to help members expand into new
  markets
• Identify and pursue new opportunities for
  technical standardization/simplification

• Established roadmap for Power Instruction Set
  Architecture (ISA)
• Platform specs and reference designs for
  embedded, servers
• SoC and software specs debug interfaces,
  embedded hypervisor, application binary
  interface, modeling simulation, Bus
  architecture report,
• Power.org Solutions Portal (online catalog of
  products services)
• Educational, networking events
• Architectural marketing PR program

Operations marketing July 05 through 2006
Expanding Value Role

• Formed committees, operating policies and work
  plans
• Expanded member base
• Created community-owned brand system
• Launched initial specs, most notably the
  converged ISA

Formation Sept. 04June 05

• Created governance model/bylaws
• Established core members, incl. Founders
• Established board of directors

Building community value
Guidance operations
Expand Power ecosystem
Launch
Evolving focus
2004
2009
2005
2006
2007
2008
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Power.orgs corporate members
Ericsson
Sony
Venture Corporation
Wistron
Celestica
End-user products
Barcelona Supercomputing Center
Curtiss-Wright Corp.
e2v
Kontron Modular Computers (Thales)
Joint Supercomputer Center
National Instruments
Shanghai Jiao Tong University
CSIP (China Ministry of Info)
Codesourcery
Terra Soft Solutions
Lynuxworks
Green Hills Software
Wind River
MontaVista Software
Software
Lauterbach
EVE
CoWare
Virtutech
Cadence Design Systems
VaST Systems
Denali Software
Synopsys
IPextreme
HCL America
Tundra Semiconductor
XGI Technology
Rapport Inc.
Silicon
Freescale Semiconductor
IBM
Joined in 2008

• AMCC

Xilinx
Plus thousands of Developer members (companies
and individuals)
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Power Architecture market leadership

• Consumer
• Core technology in the newest generation of game
  consoles (PLAYSTATION 3, Wii, X-Box 360)
• 20 million set top box processors shipped (2001
  to 2006)
• 6 million processors shipped in printers (2001
  to 2006)
• Automotive and industrial
• More than half of all new car models contain
  Power controllers (drivetrains, telematics,
  safety systems)
• Market share leader in aerospace and military
• High-performance computing
• Top architecture for supercomputing, UNIX
• Communications
• De-facto standard in telecom infrastructure
• 90 percent of wireless infrastructure market
• 50 percent enterprise/core communications markets

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Key Power Architecture advantages

• Technology Leadership and Flexibility
• Unparalleled scalability and flexibility
• Optimized for systems performance
• Proven to meet requirements of leading-edge user
  base
• Customer Choice
• Multiple vendors/suppliers
• Broad ecosystem support
• Steady ecosystem investment
• Product variety (ASSP, FPGA, soft cores, 32- or
  64-bit)
• Collaborative Innovation
• Architectural stability binary compatibility
• Shared investment leveraged to create economies
  of scale
• Open solutions and a vibrant development community

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• Technical Committee Highlights

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Power.org Technical Committee

• SoC Development
• Drive Bus standardization
• Drive SoC Design Tool Methodology
• Virtualization
• Embedded Ref Arch Platforms
• Virtualization, Firmware, Boot support
• Embedded PAPR specification to lower development
  costs
• Enable the ecosystem and
• developer community
• Multicore Enablement
• Virtualization
• Boot
• Debug
• Standard Debug Environment
• Standardization on Serial Trace
• Standardization on Logical protocol layer

• Software Arch Stack on Power
• Linux enhancements
• Multicore support
• Virtualization technologies and support
• Firmware

• Tools
• Drive modularity to support multicore new
  programming models
• Standardize on Debug APIs

Software Ecosystem
Platform Ecosystem
Solutions
Power Arch And SoC Roadmap

• Power Arch
• Drive ISA converged architecture
• Virtualization
• MMU

• SoC Cores Roadmap
• Drive competitive strategy roadmap vs. x86 and
  ARM for target markets (S/E/C)

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Power.org Technical Committee

• Our modus operandi
• We align our priorities with the priorities of
  the Eco-system and partner companies
• Judiciously chose which technical subcommittees
  to form based on an engagement and resource
  allocation plan before approving the Technical
  Sub-committee
• Objective (Technical)
• Leverage RD activities in member companies
• Pursue Power.org activities in the wider interest
  of the Power Community rather than individual
  companies.
• Build eco-system to support Power based products
  SoCs, tools, OSs etc.
• Focus on a Few Areas of High Value to the
  Eco-system and do them well

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Power.org Organization OverviewTechnical
Committee

• Board of Directors
• Councils manage architecture, operations,
  strategy
• Committees manage
• discipline areas
• Subcommittees manage projects
• Management by ISTO (IEEE)

Board of Directors FSL, IBM, Cadence, Synopsis

Power Architecture Advisory Council (PAAC)


Power Architecture Platform (Embedded) Reference
(PAPR-E) David Willoughby
ABI TWG Kate Stewart


Debug Standardization TWG Chris Ng
Embedded Hypervisor Hollis Blanchard
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Power.org 2008 Technical Subcommittees and
Workgroups

• Technical Subcommittees
• Platform Architecture TSC (ePAPR)
• Common Debug Interface TSC
• Power ABI TSC
• Embedded Hypervisor TSC
• Virtual Platforms
• Workgroups
• Software Initiatives Steering Work Group

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Power.org Technical Subcommittees and Workgroups
Platform Arch
Objective Define and publish base platform arch
standards to facilitate development of compliant
components and products
Common Debug Interface
Objective Define and maintain a set of
specifications that document a common debug
interface or a common set of debug interface
options for use in Power Architecture
implementations.
Objective Create unified ABI documents under
neutral licensing that reflect the merged Power
Architecture specification and existing coding
standards (documented and undocumented but
implemented)
Power ABI
Objective Develop hypervisor technology for
embedded Power Architecture designs, providing a
software virtualization solution, I/O
virtualization scheme and hypervisor interface
specification, among other deliverables
Embedded Hypervisor
Software Initiatives
Objective Identify gaps and initiate projects
that enhance the ecosystem supporting OS, tools,
middleware, and Applications on Power Architecture
Modeling Virtual Platform
Objective Scope proposal under development.
Concept is to adopt and/or create specifications
and standards to enable best of breed ecosystem
around ESL modeling and virtual platforms to
support pre-silicon system design assessment and
optimization and support SW application
co-development with hardware
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2008 Power.org Roadmap

• Power Night _at_ ESC
• April 16

Technical deliverables

• Power Virtual Conf
• August

• Embedded Bus Arch Report
• Apr 11
• Solutions Portal
• Apr 30

Power.org events

• PHY Connect for High-Speed Trace Spec approved
• August
• ePAPR Spec approved
• August

• Power Arch Conf
• Oct _at_ Asia
• SW Summit
• Oct _at_ Asia

• CDI API/TCF Spec
• Oct

• 32-Bit Power ABI Spec
• 2Q08

• Power ISA v2.06
• 4Q08

2008

• Power Arch Conf
• May _at_ EMEA
• SW Summit
• May _at_ EMEA

• Reference Hypervisor
• May
• Target Debug Capability Spec approved
• May 7

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• Conference Program Schedule

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Schedule for General Session - Munich
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Schedule for General Session - Paris
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Power Architecture Conference Series 2008