Multilevel Floorplanning, Placement, and Routing for LargeScale Circuits

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Multilevel Floorplanning, Placement, and Routing
for Large-Scale Circuits
??? Yao-Wen Chang ywchang_at_cc.ee.ntu.edu.tw http/
/cc.ee.ntu.edu.tw/ywchang Department of
Electrical Engineering National Taiwan University
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Outline
Multilevel Framework Basics
Multilevel Floorplanning/Placement
Multilevel Routing
Conclusion
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Outline
Multilevel Framework Basics
Multilevel Floorplanning/Placement
Multilevel Routing
Conclusion
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Moores Law Driving Technology Advances

• Moore Logic capacity doubles per IC every two
  years (1975).
• D. House Computer performance doubles every 18
  months (1975).

PentiumPro
Pentium 4
4004
80386
8086
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Why Multilevel Framework?

• Billions of transistors may be fabricated in a
  single chip for nanometer technology.
• Need tools for very large-scale designs.
• Framework evolution for CAD tools
• Flat ? Hierarchical ? Multilevel

Pentium 4 42 M Transistors (Y2000)
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Flat Routing Framework

• Sequential approaches
• Maze searching
• Line searching
• Concurrent approaches
• Network-flow based algorithms
• Linear assignment formulation
• Drawback hard to handle larger problems

Sequential
Concurrent
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Hierarchical Routing Framework

• The hierarchical approach recursively divides a
  routing region into a set of subregions and solve
  those subproblems independently.
• Drawback lack the global information for the
  interaction among subregions.

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Multilevel Routing Framework

• The multilevel framework consists of two stages
• Bottom-up the coarsening stage
• Top-down the uncoarsening stage

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Previous Multilevel Works

• Partitioning
• Alpert, Huang, Kahng, TCAD, Aug. 1998
• Karypis Kumar, DAC-99
• The results are almost good enough Cong et.
  al, ISPD-03.
• Floorplanning
• Lee, Hsu, Chang, Yang, DAC-03.
• Placement
• Chan, Cong, Kong, Shinner, ICCAD-2k.
• Routing
• Cong, Fang and Zhang, ICCAD-01.
• Lin Chang, ICCAD-02 (TCAD 2003).
• Cong, Xie, Zhang, ICCAD-02.
• Likeness
• Hybrid router Lin, Hsu, Tsai, TCAD, Feb. 1990.
• DME clock router Chao, Hsu, Ho, Boese, Kahng,
  TCS, Nov. 1992.

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Outline
Multilevel Framework Basics
Multilevel Floorplanning/Placement
Multilevel Routing
Conclusion
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Floorplan Modeling Using B-trees

• Compact modules to left and bottom (O-tree).
• Apply DFS to construct a B-tree (Chang, et al.,
  DAC-2K).
• left child adjacent, lowest-most module on the
  right.
• right child nearest module above with the same
  x-coordinate.

n0
b10
b5
b6
b3
b1
n1
n7
b4
b2
n2
n5
n8
b0
b9
n3
n6
n9
n11
b8
b11
b7
n4
n10
1-1 correspondence
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Multi-level B-trees for Floorpanning/Placement

• Coarsening (clustering)
• Iteratively groups a set of modules based on a
  cost metric.
• Establishes the geometric relations among the
  newly clustered modules.
• Uncoarsening (declustering)
• Iteratively ungroups a set of modules.
• Refines the placement/floorplanning solution
  based on simulated annealing.

G0
refined solution
projected solution
G0
G1
G2
G1
G3
G2
clustering
declustering
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Clsutering

• Given 7 primitive modules

• Cluster b5, b6, and b7 into b8 and build a
  corresponding B-tree

b8
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Clustering (contd)

• Cluster b1, b2, and b4 into b9

• Cluster b3, b8, and b9 into b10 and build a
  corresponding B-tree

b10
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Declustering

• Decluster b10 to b3, b8, and b9.

n9
n8
b8
n3

• Refine the solution by simulated annealing (move
  n8).

b8
n9
b9
n3
n8
b3
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Declustering

• Decluster b9 to b1, b2, and b4.

n1
b8
n2
n4
n3

• Simulated annealing rotate b2 and move b3.

b8
n2
n3
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Declustering

• Decluster b8 to b5, b6, and b7.

m8
n5
n2
n6
n3
n7

• Simulated annealing move b4.

m8
n5
n2
n6
n7
n4
n3
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Clustering for Soft Modules
minimize
subject to
C1 all modules must be in the chip.
C2 reshape cluster modules.
C3 reshape primitive soft modules.

• Apply Lagrangian relaxation to compute
  and

to minimize ?(x,y).
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Experiments on Large-Scale Circuits

• ami49 the largest MCNC benchmark circuit.
• ex_ami49_x created by duplicating ami49 by x
  times.
• ex_ami49_200 contains 9800 modules and 81600
  nets.
• industry a 0.18?m, 1 GHz design with 189
  modules, 20 million gates, and 9777 nets.

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CPU Time Dead Space for ex_ami49_x

• The running time of MB-tree approaches linear
  while the others cannot handle large-scale
  designs.
• The resulting dead space for MB-tree is
  consistently smaller than 3.72 while the others
  do not scale well as the circuit size increases.

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layout of ex_ami49_200

• 9800 modules, dead space 3.44, CPU time 256
  min.

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Experiments on industry

• Area optimization
• Dead space Sequence pair (14.5), B-tree_v1.0
  (9.0), MB-tree (2.1)

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Layout of industry

• Simultaneous area and wirelength optimization
• CPU time 5234 sec, Area 716.3 mm2, Dead space
  8.14, total wirelength 67786.3mm.

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Outline
Multilevel Framework Basics
Multilevel Floorplanning/Placement
Multilevel Routing
Conclusion
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Routing Model

• Partition a chip into tiles
• Multilevel routing graph G (V, E)
• Each node in V represents a tile
• Each edge in E denotes the boundary of adjacent
  tiles

multilevel routing graph
a chip
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Multilevel Routing Framework
to-be-routed net
already-routed net
Merge 2X2 tiles into a larger tile and
iteratively route nets title by tile.
Uncoarsening stage starts.
Use maze routing to route failed connections.
partitioned layout
G0
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Local Net (Connection)

• A net (connection) totally enclosed in a tile is
  called a local net (connection).
• At each level of the multilevel routing
  framework, we process tile by tile and only local
  nets in a tile are routed.

level i
level i1
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Coarsening Stage

• Build MSTs for all nets and decompose them into
  two-pin connections.
• Route local nets (connections) from level 0.
• Two-stage routing (global detailed routing) for
  a local net.

global route
detailed route
an MST edge
level k
level 0
level k
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Global Routing

• Apply pattern routing for global routing
• Use L-shaped and Z-shaped connections to route
  nets.
• Has lower time complexity than maze routing.

Upper L-Shaped connection
Z-Shaped connection
Lower L-Shaped connection
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Detailed Routing

• Via minimization
• Modify the maze router to minimize the number of
  bends.
• Local refinement
• Apply general maze routing to improve the
  detailed routing results.
• Resource estimation
• Update the edge weights of the routing graph
  after detailed routing.

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Via Minimization
Wave Propagation
Back Trace
Unrouteable Obstacle
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Local Refinement

• Local refinement improves detailed routing
  results by merging two connections which were
  decomposed from the same net.

global route
detailed route
an MST edge
level k
level 0
level k
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Resource Estimation

• Global routing cost is the summation of
  congestions of all routed edges.
• The congestion, Ce, of an edge e is defined by
• where pe and de are the capacity and
  density, respectively.
• We updates the congestion of routed edges to
  guide the subsequent global routing.

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Uncoarsening Global Routing

• Use maze routing.
• Iterative refinement of a failed net is stop when
  a route is found or several tries have been made.

Uncoarsening stage
Coarsening stage
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Multilevel Routing Summary

• Coarsening
• Global routing Pattern (L-shaped) routing
• Detailed routing Maze routing
• Refinement Z-shaped global routing Detailed
  Maze routing
• Uncoarsening
• Global routing Maze routing
• Detailed routing Maze routing
• Refinement Maze global routing Detailed Maze
  routing

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The Benchmark Circuits

• Provided by the UCLA VLSI CAD Lab.

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Routing Comparisions

• Ours obtain 100 completion rates for all
  benchmarks.

(A)(B)(C) Ultra-5 440MHz 384MB (D) Ultra-60 450
MHz 2GMB
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Routing Result for Prim2
Use 2 layers (completion rates 100)
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Routing Results for S38584
Completion rates 93.7 with timing
optimization layers 1 2
With timing optimization Dmax 129267 ps,
Davg 739 ps
Without timing optimization Dmax 1.75 108 ps,
Davg 13799 ps
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Routing Results for S38584
The 3rd layer
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Outline
Multilevel Framework Basics
Multilevel Floorplanning/Placement
Multilevel Routing
Conclusion
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Conclusion

• The multilevel framework is effective for
  handling large-scale floorplanning/placement/routi
  ng
• Other potential multilevel research directions
• Mixed-sized large-scale cell/module
  floorplanning/placement
• Large-scale routing considering various
  constraints (e.g., crosstalk, EM, etc)
• Large-scale power/ground line synthesis
• Large-scale clock-tree synthesis
• Multilevel frameworks for logic synthesis,
  verification, testing, simulation, extraction?

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Thank You