Design and Simulation of a Low Power Rake Receiver for Indoor Communication - PowerPoint PPT Presentation

About This Presentation
Title:

Design and Simulation of a Low Power Rake Receiver for Indoor Communication

Description:

Design and Simulation of a Low Power Rake Receiver for Indoor ... De-Rotator. NCO. Accumulator. Phase Error. Detector. Loop. Filter. Initial Frequency Offset ... – PowerPoint PPT presentation

Number of Views:429
Avg rating:3.0/5.0
Slides: 33
Provided by: Mati159
Category:

less

Transcript and Presenter's Notes

Title: Design and Simulation of a Low Power Rake Receiver for Indoor Communication


1
Design and Simulation of a Low Power Rake
Receiver for Indoor Communication
  • Advisor Tzi-Dar Chiueh
  • Student Po-An Chen
  • Date Mar 7th , 2005

2
Outline
  • Introduction
  • Background of Rake Receiver
  • Goal
  • System Architecture
  • System Specification
  • Channel Model
  • Packet Format
  • Architecture
  • Operation Flow
  • System Simulation
  • Receiver Performance
  • Fixed-Point Simulation
  • Conclusion
  • Reference

3
Introduction
4
Background of Rake Receiver(1)
  • Spread Spectrum Basics
  • Transmitting signal using wider bandwidth than
    necessary
  • A spreading code is used at Tx and Rx to spread
    signals
  • Direct Sequence (DSSS) vs Frequency Hop (FHSS)

a
b
a
b
c
c
d
d
1
5
Background of Rake Receiver(2)
  • Multi-path fading is a severe non-ideality
    inherent in typical wireless channel
  • For DSSS system, Rake Receiver provides time
    diversity by combining signal at different
    timings

From Marcel
Multi-path scenario
6
Background of Rake Receiver(3)
  • In the NSC_BIST 5GHz project, a low power DSSS
    receiver is required
  • A DSSS receiver alone cannot resolve multi-path
    fading

2
7
Background of Rake Receiver(4)
  • Conventional Rake Receiver consumes high power
  • 4.1mW _at_ 20MHz clock rate
  • Optimal number of Rake finger decision rule has
    been proposed in
  • LOS
  • Fingers lt 4
  • NLOS
  • Fingers lt 13

3
4
8
Background of Rake Receiver(5)
  • Minimum sampling timing spacing of fingers cannot
    be smaller than inverse of the chip rate
  • Fractionally-spaced yields advantage over
    chip-spaced
  • Signal bandwidth gt chip rate
  • -gt reducing sampling spacing outperforms
    integer sampling spacing
  • Architectures for fractionally-spaced Rake has
    been proposed in
  • Hardware cost increase
  • Clock rate increase

5
integer
fractional
6
stronger
lower
Chip rate 16MHz
T1 T2
T1 T2
T1- T2 1/16MHz
T1- T2 1/16MHz
9
Goal
  • A low power solution for Rake Receiver
  • A fractionally-spaced Rake with low hardware cost
  • A receiver capable of combating indoor multi-path
    fading

Channel estimation
Weighting
Finger 1
?
Finger 2
Finger 3
From Jui- Ping Lien
Rake receiver
Combining (MRC)
10
System Architecture
11
System Specification
  • Chip rate 16MHz
  • PN sequence length 32
  • Data rate 1Mbps
  • Modulation QPSK
  • CFO /- 20ppm
  • RF frequency 5GHz
  • System Clock 16MHz
  • 8 chips per partial correlation
  • ADC output 64MHz
  • A 4-phase DLL
  • Rake finger number - 3
  • Power consumption lt 3mW

2
12
Channel Model
  • 5GHz narrowband channel model based on 802.11a
  • TDL model with inverse of 256MHz tap spacing
  • Delay Spread
  • 10ns, 20ns, 60ns considered
  • Doppler Spread
  • Around 30 Hz
  • CFO effect
  • Maximum relative CFO is 40ppm
  • 5GHz 40ppm 200 kHz
  • 200/500 -gt 36o per partial correlation output

13
Packet Format
120 Symbols Preamble
8 Symbols Data Start
1024 Symbols Data
  • Preamble
  • Coarse CFO estimation
  • PN code acquisition
  • Path search
  • Channel estimation
  • Data Start
  • Define data start timing

8
14
Architecture(1)
  • Proposed Receiver

8
Digital
Analog
15
Architecture(2)
  • Conventional Rake Receiver

W1
W2
W3
9
16
Architecture(3)
  • Proposed Rake Receiver
  • correlator move behind multipliers
  • 3 fingers adopted

W1
W2
W3
17
Architecture(4)
  • Implementation of Rake Receiver
  • DLL required

W1
DFF
W2
Signal
DFF
W3
DFF
Clock from DLL controlled by digital circuit
while consuming additional 0.5mW power
18
Operation Flow
  • DLL start
  • Multi-phase clock
  • Coarse CFO estimation
  • Due to large amount of CFO
  • PN code acquisition
  • Path search
  • Find combine path timing
  • Channel estimation
  • Determine path gain
  • Rake start
  • Data recovery

19
Operation Flow(1)
  • DLL start

20
Operation Flow(2)
  • Coarse CFO estimation

21
Operation Flow(3)
  • PN code acquisition
  • Path search
  • Channel estimation

22
Operation Flow(4)
  • Rake start Data recovery

23
System Simulation
24
Receiver Performance(1)
  • Performance under different channel delay spread

25
Receiver Performance(2)
  • Performance with/without Rake receiver

26
Receiver Performance(3)
  • Performance of different finger sampling timing
    spacing

27
Receiver Performance(4)
  • QPSK Constellation

10ns
60ns
With Rake
Without Rake
28
Fixed-Point Simulation(1)
  • ADC output bit length

ADC output
29
Fixed-Point Simulation(2)
  • Rake Receiver Output Bit Length

30
Fixed-Point Simulation(3)
  • CFO Loop
  • Not finished yet
  • 5-Path Pre-Carrier Recovery Circuit
  • Not finished yet

9 bit
7 bit
31
Conclusion
  • A low power DSSS Rake Receiver has been proposed
    and simulated
  • A DLL is used to implement fractionally spaced
    Rake Receiver effectively
  • System ability of resolving multi-path fading
    justifies the need for fractionally-spaced finger
    sampling spacing

32
Reference
  • 1 Communication System, Simon Haykin
  • 2 NSC_BIST ????
  • 3Ahmed M. Eltawil and Babak Daneshrad, A
    Low-Power DS-CDMA RAKE Receiver Utilizing
    Resource Allocation Techniques, IEEE JSSC, vol.
    39, Aug. 2004.
  • 4Chi-Min Li and Hsueh-Jyh Li, A Novel RAKE
    Receiver Finger Number Decision Rule, IEEE
    Antennas and Wireless Propagation Letters, vol
    2., 2003
  • 5 K.J. Kim, et al., Effect of Tap Spacing on
    the Performance of Direct-Sequence
    Spread-Spectrum RAKE Receiver, IEEE Trans.
    Commun., vol. 48, June 2000
  • 6P.Sehier and P. Brelivet, Performance
    evaluation of an oversampled Rake receiver, in
    Proc. IEEE MILCOM, vol. 2, 1994.
  • 7 P802-15_SG3a-Channel-Modeling Final accept
    revision
  • 8 NSC_BIST ????
  • 9????????
Write a Comment
User Comments (0)
About PowerShow.com