Clock Networks and PLLs in Alteras Stratix III Devices

1
Clock Networks and PLLs in Alteras Stratix III
Devices

• VLSI Systems I
• Fall 2007
• Hamid Abbaalizadeh

2
Clock Resources in Stratix III Devices

• Global clocks (GCLKs), Regional Clocks (RCLKs),
  and Peripheral Clocks (PCLKs) are organized into
  hierarchical structures that provides 220 unique
  clock domains.
• 16 low skew GCLKs drive functional blocks like
  DSP and PLL
• Maximum of 88 low skew and low delay RCLKs drive
  logic.
• 116 higher skew PCLKs can be used as general
  purpose routing to drive signals into and out of
  the device.

3
Global and Regional Clock network and Clock
Control Blocks
4
PPLs in Stratix III

• Up to 12 PLLs that provides robust clock
  management

5
De-skewing by PLL

• Phase Frequency Detector (PFD) method is used for
  clock alignments.
• Charge Pump (CP) drives the current to Loop
  Filter (LF) if it receives an up signal. If it
  gets down signal, CP sinks the current from LF.
• Voltage Controlled Oscillator (VCO) is biased by
  LF.
• LF also eliminates the glitches and prevents the
  overshoot, which the jitter on the VCO.

6
Features

• Maximum internal clock speed 600 MHz
• On chip RAM 600 MHz
• DSP block speed 550 MHz
• PFD method in the PLLs is used to de-skew the
  clocks

7
PLLs Features