10Gbs Optical Data Links With DSPBased Dispersion Compensation

1
10Gb/s Optical Data Links WithDSP-Based
Dispersion Compensation

• Norman L. Swenson
• ClariPhy Communications, Irvine, CA
• ISSCC 2008
• 5 February 2008

2
Trends in High-Volume Phy ICs

• Historically, high volume Phy ICs trend toward
  all-CMOS, all-digital
  
• Reasons Performance, Reliability,
  Manufacturability, Integration
  
• This talk explores whether a similar transition
  can/will occur in 10G multimode fiber optical
  networking

3
Overview

• The Multimode Fiber Channel (10GBASE-LRM)
• EDC Structures
• Analog versus Digital
• State of the Art

4
The Multimode Fiber Channel
5
The 10GBASE-LRM Application

• High-volume enterprise applications
• Data center and building infrastructure
• 220m (300m desired) of legacy (FDDI grade)
  multimode fiber (MMF)
  
• Emphasis on low-cost, low-power for multi-port
  designs

10GBASE-LRM is defined in 1
6
MMF Channel Impairments

• Dispersion is primarily modal dispersion
• Multiple modes excited, with different group
  velocities
  
• Large variation in transit times for different
  modes
  
• Net result Superposition creates linear
  intersymbol interference (ISI)
  
• Nonlinearity can be introduced by TIA
• ISI can vary greatly with fiber movement, stress,
  connector mating, etc.
  

Some typical MMF Responses (See 2)
7
EDC Structures
8
Feed-Forward Equalizer (FFE)

• Advantages
• Simple
• Can be realized in analog or digital

• Disadvantages
• Very long length rqd
• Noise enhancement
• Insufficient for LRM channel

9
Decision Feedback Equalizer (DFE)

• Advantages
• No noise enhancement
• Can be realized in analog or digital
• Can be designed to mitigate nonlinear effects

• Disadvantages
• Sub-optimal (wastes signal energy)
• Difficult latency issue for feedback path
• Error Propagation

10
Maximum Likelihood Sequence Detection (MLSD)

• Advantages
• Theoretically optimal design
• Makes use of all of received signal energy
• Can be designed to mitigate nonlinear effects

• Disadvantages
• Complexity
• Requires digital implementation(At least for the
  back end)
  

11
Analog versus Digital
12
Implementation Alternatives

• Three alternatives
• All-analog, analog with digital control, all
  digital
  
• All topologies make use of a feed-forward filter
  front end
  
• FFE conveniently illustrates tradeoffs

13
All-Analog FFE
D
D
D
Analog SignalPath
c-2
c-1
c0
c-3
S

• Analog Signal Path
• Summers
• Multipliers
• Delay line

• Analog Signal Path Challenges
• Accuracy limitations of arithmetic elements
• Signal degradation with increased delay line
  length

See, for example, 3-4 for an analog FFE (no
automated control)
14
All-Analog FFE
AnalogControl
D
D
D
Analog SignalPath
c-2
c-1
c0
S

• Analog Control
• LMS (see c-3 coeff)
• AGC
• Baseline wander compensation
• Clock recovery
• Offset compensation

• Analog Control Challenges
• Inaccuracy of analog integration can cause LMS to
  misconverge
  
• Accuracy limitations of arithmetic elements

See, for example, 5 for an analog DFE with
analog LMS control
15
Digital ControlAnalog Signal Path
rn
rn-1
rn-2
rn-3
D
D
D
en
Digital
D
D
D
S
Analog
-

c-2
c-1
c0
c-3
S

• Analog path for signal, as before
• Signal is digitized and digitally processed to
  generate control signals
  
• Processing is at slower rate than data rate
• Problems
• Signal ADC shown has to sample at full data rate
  to generate sequential samples for LMS algorithm
  
• Mismatch between digital delay line and analog
  delay line

Coefficients
DSP for LMS, AGC, Clock Recovery, Offset Comp.
Gain Control
en
Clock Control
Offset
16
Digital ControlAnalog Signal Path
en
Digital
D
D
D
S
Analog
-

c-2
c-1
c0
c-3
S

• Replace single sampler and delay line with
  multiple samplers
  
• Samplers run at sub-rate
• Must still be high bandwidth, short sampling
  window (e.g.,
  
• Problems
• Number of samplers grows with length of tapped
  delay line
  
• Analog signal path still degrades signal
• Samplers further load delay line, worsening
  degradation

Coefficients
DSP for LMS, AGC, Clock Recovery, Offset Comp.
Gain Control
en
Clock Control
Offset
17
All-Digital
Subsample
en
Digital
D
D
D
AFE
S
Analog
-

c-2
c-1
c0
c-3
S

• After Analog Front End, signal is digitized and
  all signal processing is digital
  
• Signal is subsampled and control signals (LMS,
  timing recovery, etc.) are generated at lower
  rate
  
• Challenges
• Low power CMOS ADC at 10 Gsample/sec and5
  ENOB
  
• Architecture of FFE and backend (DFE or MLSD) to
  process signal at 10 Gsym/sec

Coefficients
DSP for LMS, AGC, Clock Recovery, Offset Comp.
Gain Control
en
Clock Control
Offset
18
Solutions forHigh-Speed Digital Processing

• ADC
• 8-way interleave reduces clock to 1.3 GHz on each
  ADC channel
  
• Pipeline architecture with open-loop residue
  amplifiers reduces power consumption
  
• FFE architecture
• Feed-forward structure allows parallelism,
  pipelining to reduce speed requirements
  
• Backend architecture
• MLSD realized with feed-forward structure via
  Sliding Block Viterbi Decoder
  
• For example, window of 32 samples processes 16
  samples, then slides over 16 samples
  
• 8 samples at beginning and end of window are used
  to initialize state metrics for bi-directional
  processing
  

r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
r r r r
19
24-Bit Sliding Block Viterbi Example
Detection
Synch
Synch
20
24-Bit Sliding Block Viterbi Example
Detection
Synch
Synch
21
24-Bit Sliding Block Viterbi Example
Detection
Synch
Synch
22
State-of-the-Art
23
All Digital 90nm CMOSMLSD Transceiver

• See ISSCC 08 Paper 11.7 7 and Design Forum F5
  8

24
Conclusions

• CMOS DSP-based EDC designs offer several
  advantages
  
• Design predictability, manufacturability,
  integration, reliability
  
• Significantly improved performance
• They also present unique implementation
  challenges at these speeds
  
• With novel architectures, advanced ADC
  techniques, and shrinking linewidths, DSP-based
  approaches can be practically realized
  
• The path is paved for 10G MMF EDC to follow the
  leads of other large market PHYs and migrate to
  an all-digital CMOS solution
  

25
References

• IEEE Standard 802.3AQ-2006, Physical Layer and
  Management Parameters for 10Gb/s Operation Type
  10GBASE-LRM, Sept.2006
  
• 108 Fiber Model, IEEE802.3AQ Task Force,
  Oct.2004
  
• H. Wu, et al, Differential 4-tap and 7-tap
  Transverse Filters in SiGe for 10Gb/s Multimode
  Fiber Optic Link Equalization, ISSCC 2003
  
• P. Pepeljugoski, et al, Improved performance of
  10 Gb/s multimode fiber optic links using
  equalization, Optical Fiber Communications
  Conference, 2003. OFC 2003
• D. McPherson, et al, A 10 Gb/s adaptive
  equalizer with integrated clock and data recovery
  for optical transmission systems, Optical Fiber
  Communication Conference, 2005. Technical Digest.
  OFC/NFOEC
• P. Black and T. Meng, A 1Gb/s four-state,
  sliding block Viterbi decoder, IEEE J.
  Solid-State Circuits, Vol.32, pp.797-805, June
  1997.
• O. Agazzi, et al, A 90nm CMOS DSP MLSD
  Transceiver with Integrated AFE for Electronic
  Dispersion Compensation of Multi-mode Optical
  Fibers at 10Gb/s, ISSCC 2008, Paper 11.7
• O. Agazzi, DSP-Based Optical Transceivers for
  Electronic Dispersion Compensation of Single-Mode
  and Multimode Fibers, ISSCC 2008, Design Forum F5

Acknowledgment
Oscar Agazzi is gratefully acknowledged for
helpful discussions contributing to this
presentation.
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