Timingaware power noise reduction using prediction and correction

1
Timing-aware power noise reduction using
prediction and correction

• Malgorzata Marek-Sadowska
• University of California, Santa Barbara

Chao-Yang Yeh Apache Design Solutions
2
Outline

• Motivation
• Previous work
• Background
• Prediction
• Neighborhood-aware decap allocation
• Correction
• Gate sizing for power noise and timing
• Experiments
• Conclusion

3
Motivation

• Power noise is a serious problem

20
16.7
0.3V
0.3V
0V
1.5V
1.8V
0V

• Power noise affects timing and even function

Cell delay
Voltage drop

• Decap is useful to reduce power noise
• Decap location has to be selected wisely

4
Decap allocation problem

• How to allocate decaps among individual blocks of
  a floorplan?

Decap
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Previous work

• Optimization during placement
• increases placement complexity
• lacks a global view at the early placement
  iterations
• Post-layout decap re-allocation
• Large decap re-allocation unattractive

Decap
Previous decap-allocation works do not consider
timing
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Proposed flow prediction and correction
Decap padding
Prediction
Cell decap padding assignment
( Reduce decap re-allocation )
Cell
Decap
Neighborhood Prediction
Placement Grid analysis
Gate sizing
Correction
Gate sizing for power noise and timing
( Use pad location/ grid information )
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Power grid/decap modeling (I)

• Regular power grid/pad distribution
• Uniformly partition of the chip

One partition
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Power grid/decap modeling (II)

• For one partition

• Lumped decap

Cell decap
Inserted decap

• Lumped current source

current
te
1ns
ts
time
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The prediction step

• Decap allocation

Decap padding
Decap_weight(n)

• Compute neighborhood current consumption (NCC)

n
Noise_weight(n)
( More noisy, more padding )
neighborhood

Timing_weight(n)
( More critical, less padding )
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Wirelength Prediction background Mutual
contraction
B. Ho, M. M. Sadowska, DAC03

• Based on circuit topology analysis
• Compute contraction weight
• Only predict distance between cells that have
  connections

Mutual contraction MC(x, y) Wr(x, y) Wr(y, x)
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Mutual contraction in different placers

• Works for general wirelength-driven placers

Dragon
FengShui
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Neighborhood levels
n
0-th level Neighbors
1-st level Neighbors
(i1)-th level Neighbors
Cells with short connections to
Higher level neighbors, larger neighborhood area
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Neighborhood current consumption (NCC)

• Higher level NCC, more cells involved

• 0-th level NCC
• (Individual cell current consumption)

• i-th level NCC

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Neighborhood current consumption (NCC)
Neighborhood levels
Level NCC computation
2-nd
c
11
1-st
b
5
9
0-th
n
d
10
a
8
e
2
8
2
5
8
9
10
8
9
Higher level NCC -gt Less highly switching cells
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Noise/timing weight
Decap_weight noise_weight timing_weight

• Noise weight

• Timing weight

Noise/timing weight in the range 01
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Decap allocation

• Decap weight

Timing scale

• Decap width

Total decap area
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Prediction experiment (I)
Benchmark ex1010
(b)
(a)
NCC Level 1
NCC Level 0
55 cells
NCC Level 4
NCC Level 2
(d)
(c)
Decap will be allocated to those highly switching
cells
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Prediction experiment (II)

• Simulation results (Vdd 1.8v)

Decap EVEN
Decap WGT, NCC level 4
(a)
(b)
Min V1.64
Min V1.72
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Correction step gate sizing

• After placement and grid simulation
• Do gate sizing
• Re-allocate decaps
• Meet timing constraints
• Sequence of linear programs (SLP)
• Solve a linear programming (LP) problem in each
  iteration

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Linear programming (LP) problem formulation
LP constraints
Divide chip into blocks

Timing_const
Minimize

Power consumption cost
Noise_const

Area_const
Noise cost
Noise cost factor
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LP timing constraints

• Using gain-based delay model

• Cell delay function

Cell power voltage
Size of cell k
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LP timing constraints (cont)

• Using Taylors expansion

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Experimental setup

• Ideal chip voltage 1.8V
• MCNC benchmarks (cell 419923362)
• 0.18um technology
• Decap area 20 of total cell area
• 5 Vdd voltage noise margin
• Linux Pentium 2.4GHz

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Experiment flow
Prediction Allocate decap
Correction Gate sizing
Placement
Grid analysis
Grid analysis
Results after prediction optimization
Results after correction optimization
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Power noise measurement metrics

• 5 voltage drop margin
• Metrics
• Worst voltage drop (IRV)
• Violation count (vioC)
• Sum of excess noise area (SENA)

Voltage
Vdd
95 Vdd
Excess noise area
time
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Experimental results prediction

• Results after prediction optimization

NOC no decap, EVEN even decap distribution,
WGT predictive method
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Experimental results correction

• Results after correction optimization

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Experimental results voltage drop

• TS0, optimize power noise only

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Power noise reduction conclusion

• Proposed a flow for power noise reduction
• Timing-aware power noise reduction
• Prediction - correction flow
• Prediction neighborhood prediction
• Correction gate sizing for noise and timing
• Proposed techniques are effective and efficient
• Effective even without decap insertion

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Experimental results prediction (cont)

• Timing results after optimization