SiFMD

1
Si-FMD

• Update on Status
• Conceptual design of FEE and BEE-DAQ chain
• Timetable
• Heat dissipation

2
Hybrid with Viking PA chips
Connector(s) for power, control, read-out

• Hybrid cards contain
• FEPreampl. chips
• Bias voltages distribution
• Gate/strobe distribution
• Read-out clock distribution
• Detector bias connection

Other components
VA preampshaper 128 ch
Si detector
3
FMD RO strategy
4
FMD FEE test setup
Labview DAQ
5
Si-FMD timetable (1)
6
Si-FMD timetable (2)
7
FMD Material constants (1)
Material type and thickness of one Si detector
ring
8
FMD Material constants (2)
Material type and thickness of one Si detector
ring
Total thickness of one Si ring C
5.2 10-3 ?I 1.8 10-2 X0

Al 5.1 10-3 ?I 2.4
10-2 X0
9
Heat dissipation. Si-FMD
Heat dissipated by FE electronics of one Si
detector ring
VA1TA preamp chip (128 channels) 150 mW
? 80 chips 12 W / ring For
simulation assume uniform distribution on
hybrid surface (towards
support plate) Read-out electronics and power
distribution ? 5 W / ring For simulation
assume concentrated in 2 locations near outer
radius gt Total estimated heat release pr . side
lt 30-40 W
10
FMD electronics
FMD channel count
Note We are looking into increasing the number
of strips, but use more integrated FE
chips - red values.
11
FWD detectors