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BDDbased Logic Synthesis for LUTbased FPGAs

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Mark critical nodes. Collapse critical path. Blif N/W. Build BDDs. sweep. Yes. No. Delay ... Main goal is to utilize the sharing between the different outputs ... – PowerPoint PPT presentation

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Title: BDDbased Logic Synthesis for LUTbased FPGAs


1
BDD-based Logic Synthesis for LUT-based FPGAs
  • Submitted to ACM Trans. On Design Automation by
    Navin Vemuri, et al.
  • Presented by
  • Kesava R. Talupuru

2
Outline
  • Introduction
  • BDD based functional decomposition
  • BDS-pga synthesis flow
  • Results of BDS-pga
  • My project (decomposition for multiple output
    functions)

3
Introduction
  • Combinational Boolean Network represented by
    DAG (Directed Acyclic Graph)
  • Depth of a Node Number of edges on the longest
    path from primary input to the node
  • Support set of variables that Boolean
    expression F explicitly depends on, i.e. fanin of
    that node
  • Fanin cone Cv rooted at v connected subnetwork
    consisting of v and its predecessors

4
Introduction Contd
  • Fanout free cone sub network where no node in
    the cone is connected to nodes not in the cone
  • Maximum fanout free cone maximum allowable
    nodes without violating the fanout condition
  • K-feasible node node which has no more than k
    inputs

5
BDD-based Functional Decomposition
  • Theory of Dominators forms the basis

6
Example of Boolean Division
D e d
F e bd
e
e
d
d
Q e b
0
1
e
b
b
0
1
0
1
7
BDD-based decomposition for FPGA synthesis
  • BDS efficiently identify both AND/OR and AND/XOR
  • XOR identification significantly reduces
    implementation resources
  • Unlike standard cell designs, decomposition for
    LUT-based FPGAs depends on the number of inputs
    to, and not the functionality of, the decomposed
    nodes

8
Comparision of results for sis Flowmap and
BDSFlowmap
Numbers represent the Number of LUTs used to
represent the design
9
Framework of BDS-pga Synthesis flow
Blif N/W
Delay re-synthesis
Mark critical nodes
Build BDDs
Collapse critical path
sweep
MFFC-based iterative eliminate
Simplify logic
Greedy/Heuristic Decomposition by variable
partitioning
All BDDs Decomposed ?
Tech-Mapping
Decomposed nodes k feasible ?
Yes
No
10
MFFC-based iterative eliminate
outputs
outputs
inputs
inputs
11
Greedy Variable Partitioning Algorithm
O
S
Q
A
A
A
B
B
C
C
1
0
D
D
E
E
F
O abcdadef
F
1
0
0
1
12
Heuristic Variable partitioning for Area
a
a
swap
b
b
b
swap
c
c
e
e
d
d
d
d
e
e
c
f
f
0
1
0
1
13
Comparison of Greedy Area-Minimal Heuristic
14
BDS based Logic synthesis (targeting FPGAs) for
multiple output functions
  • Main goal is to utilize the sharing between the
    different outputs
  • This sharing helps in the reduction of total
    number of LUTs required to represent the circuit.
    This reduces the total area
  • All output functions are build with the same
    variable ordering
  • A cut is placed at the same level for each output
    function. This significantly helps in sharing the
    commonalities
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