PHENIX upgrade DAQ Status HBD FEM experience so far

1
PHENIX upgrade DAQ Status/ HBD FEM experience (so
far)

• The thoughts on the PHENIX DAQ upgrade
• Slow download
• HBD test experience so far
• GTM
• FEM readout (DCM)

2
Ethernet in PHENIX Upgrades

• For the next generation of PHENIX FEMs, Steve
  Boose has been working on selecting an Ethernet
  based controller same basic features as GAB, but
  additional capabilities possible, like an
  additional slow path for reading data
• Desirable features
• Small footprint, low profile (to fit in VME slot
  spacing 0.7 in)
• Enough CPU and memory to handle ethernet traffic
  and control
• Comfortable development environment
• Open design so that schematics can be dropped
  into designs
• Some disadvantages
• Fatter cable connectors probably have to be
  bigger RJ45
• More software complexity
• Point-to-point wiring and hubs necessary
• Current best idea is Freescales Motorola
  Coldfire 5282 board
• Schematic freely published free binary monitor
  (RTXC)
• Linux inside http//www.uclinux.org/ports/coldfi
  re/
• About 300

CML-5282 Motorola Coldfire development board
(3.5x4) (www.axman.com)
3
Optical out Design is done -- checking New DCM
daughter card design is done -- checkinh For
Clockmaster, clock fanout, ADC and backplane, the
prototype boards are assembled
Updated HBD FEM Diagram
Crate
Backplane
(7 blank boards, 4 crates 1 spare 2 test stands)
(7 blank boards, 4 crates 1 spare 2 test stands)
Clock fanout
ADC
Optical out
Test pulse
(25 blank boards. We have major of the parts for
5 boards)
(4 blank boards, 1 needed 1 spare 2 test
stands)
Clock Master
New Daughter card DCM
GTM/Ethernet
4
Clock Master Board

• About Freescale coldfire evaluation board
• 40 MHz system clock worry about trace length to
  FPGA
• Data/clock/address looks ok on scope
• Come with TCP/IP software
• So far --- Low performance
• Commercial software expensive

Freescale Coldfire Evaluation board
Analog Device Blackfin processor has similar
device -- it has a system core group Support
uclinux tcp/ip software
Serial data In/out
GTM Input
Clock Circuits
5
GTM interface

• GTM optical interface provides
• 4x beam clock ? via recover link clock
• RHIC beam clock depend on collision species
• L0 timing , L1 trigger
• In the GLINK data word
• New optical protocol (8b/10b encoding) requires
  reference clock on the receiver end within 100ppm
  of the transmitter clock.
• it is not practical to transfer the clock using
  the new optical protocol
• For the upgrade program, we will stay with old
  GTM interface.
• We may have a revised version of current GTM but
  using the old optical protocol.

6
FEM can hold up to 5 L1 events The DCM performs
zero suppression, data formatting, multiple
event buffer, generating BUSY, and error
checking. DCM has to provide 5 L1 event buffer
for FEM First Stage of the event building
First Generation DCM
Data from FEM
Zero suppression daughter card
DSP
Zero suppression daughter card
DSP
Zero suppression daughter card
DSP
DSP
Zero suppression daughter card
DSP 40 MHz 32 bits
32 bits 40 MHz
Average zero suppression factor is 40 for
Au-Au mini-bias
Zero suppression daughter card
DSP
Zero suppression daughter card
DSP
Zero suppression daughter card
DSP
DSP
Zero suppression daughter card
DSP 40 MHz 32 bits
Partition Module
We have roughly 200 DCM modules 23 DCM crates.
7
New DCM Daughter Card
Before the new DCM exist, this new DCM daughter
card can use to read out new detectors FEM with
old DCM Module.
8b/10b encoding on the optics data stream 16 bits
raw data Fix 1.6 Gbits data link
Optical Transceiver
80 MHz optical clock reference
Altera Stratix GX FPGA (de-serializer, zero
suppression, buffer etc)
Data Flow