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Memories, Part I

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Palm. Nonvolatile. ROM. Flash memories. Magnetic memories like disk, tape. Spring 2003 ... Reading. Tank had a 1 value raises water level ... – PowerPoint PPT presentation

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Title: Memories, Part I


1
Memories, Part I
  • Anselmo Lastra

2
Topics
  • Random-Access Memory
  • Static
  • Dynamic

3
Memories in General
  • Computers have mostly RAM
  • ROM (or equivalent) needed to boot
  • ROM is in same class as Programmable Logic
    Devices (PLDs), in which are also FPGAs
  • Lots of memories in these devices

4
Properties of Memory
  • Volatile
  • Memory disappears if power goes out
  • Typical computer RAM
  • Palm
  • Nonvolatile
  • ROM
  • Flash memories
  • Magnetic memories like disk, tape

5
Random Access Memories
  • So called because it takes same amount of time to
    address any particular part
  • Unlike tapes
  • Even disks

6
Simple View of RAM
  • Of some word size n
  • Some capacity 2k
  • k bits of address line
  • Maybe have read line
  • Have a write line

7
1K x 16 memory
  • Variety of sizes
  • From 1-bit wide
  • Issue is no. of pins
  • Memory size specified in bytes
  • This would be 2KB memory
  • 10 address lines and 16 data lines

8
Writing
  • Sequence of steps
  • Setup address lines
  • Setup data lines
  • Activate write line (maybe a pos edge)

9
Reading
  • Steps
  • Setup address lines
  • Activate read line
  • Data available after specified amt of time

10
Chip Select
  • Usually a line to enable the chip
  • Why?

11
Writing
12
Reading
13
Static vs Dynamic RAM
  • SRAM vs DRAM
  • DRAM stores charge in capacitor
  • Disappears over short period of time
  • Must be refreshed
  • SRAM easier to use
  • Faster
  • More expensive per bit
  • Smaller sizes

14
Structure of SRAM
  • Control logic
  • One memory cell per bit
  • Cell consists of one or more transistors
  • Not really a latch made of logic
  • Logic equivalent

15
Bit Slice
  • Cells connected to form 1 bit position
  • Word select gates one latch from address lines
  • Note it selects Reads also
  • B (and B not) set by R/W, Data In and BitSelect
  • Funny thing here when you write. What is it?

16
Bit Slice can Become Module
  • Basically bit slice is a X1 memory
  • Next

17
16 X 1 RAM
  • Now shows decoder

What is this?
18
Tri-State
  • Have three states H, L, and Hi-Z
  • High impedance
  • Behaves line no output connection if in Hi-Z
    state
  • Allows connecting multiple outputs

19
Multiplexed with Hi-Z
  • Normal behavior is blue area

Smoke
20
Row/Column
  • If RAM gets large, there is a large decoder
  • Also run into chip layout issues
  • Larger memories usually 2D in a matrix layout
  • Next Slide

21
16 X 1 as 4 X 4 Array
  • Two decoders
  • Row
  • Column
  • Address just broken up
  • Not visible from outside

22
Change to 4 X 2 RAM
  • Minor change in logic
  • Also pinouts
  • Try addressing 011 on board

23
Realistic Sizes
  • Imagine 256K memory as 32K X 8
  • One column layout would need 15-bit decoder with
    32K outputs!
  • Can make a square layout with 9-bit row and 6-bit
    column decoders

24
SRAM Performance
  • Current ones have cycle times in low nanoseconds
    (say 2.5ns)
  • Used as cache (typically offchip secondary cache)
  • Sizes up to 8Mbit or so for fast chips

25
Dynamic RAM
  • Capacitor can hold charge
  • Transistor acts as gate
  • No charge is a 0
  • Can close switch add charge to store a 1
  • Then open switch (disconnect)
  • Can read by closing switch
  • Sense amps

26
Hydraulic Analogy
Storage Full (1) Empty (0)
Pump fills tank to 1 value
Pump drains tank to 0 value
27
Reading
Outside water begins at intermediate level (black
wavy line)
Tank had a 1 value raises water level
Tank had a 0 value lowers water level
28
DRAM Characteristics
  • Destructive Read
  • When cell read, charge removed
  • Must be restored after a read
  • Refresh
  • Also, theres steady leakage
  • Charge must be restored periodically

29
DRAM Logical Diagram
30
DRAM Read Signaling
  • Lower pin count by using same pins for row and
    column addresses

Delay until data available
31
DRAM Write Timing
32
DRAM Refresh
  • Many strategies
  • Logic on chip
  • Here a row counter

33
CAS Before RAS
  • Set column address
  • Apply CAS first (opposite of RW)
  • Then toggle RAS enough times to cycle through row
    addresses
  • On-board refresh counter applies the row addresses

34
Timing
  • Say need to refresh every 64ms
  • Distributed refresh
  • Spread refresh out evenly over 64ms
  • Say on a 4Mx4 DRAM, refresh every 64ms/409615.6
    us
  • Total time spent is 0.25ms, but spread
  • Burst refresh
  • Same 0.25ms, but all at once
  • May not be good in a computer system
  • Refresh takes low of total time

35
Larger/Wider Memories
  • Made up from sets of chips
  • Consider a 64K by 8 RAM
  • Note new symbols for sets of lines, 8 16 bits
    wide

36
Larger
  • 256K X 8
  • Decoder for high-order 2 bits
  • Selects chip
  • Look at selection logic
  • Address ranges
  • Tri-state outputs

37
Wider 64K X 16
38
Bidirectional Lines
  • Many chips have one set of data pins
  • Used as input for write
  • As output for read
  • Tri-state
  • Makes sense because dont need both at once

39
Page Mode DRAM
  • Modern computers always use cache
  • DRAMs made to read write blocks
  • Example
  • Assert RAS, leave asserted
  • Assert CAS multiple times to read sequence of
    data
  • Similar for writes

40
Synchronous DRAM (SDRAM)
  • Has a clock!
  • Common type in PCs late-90s
  • Multiple banks
  • Pipelined
  • Start read in one bank after another
  • Come back and read the resulting values one after
    another

41
SDRAM on Xess Board
  • Relatively small at 128Kbits
  • 2M X 4 banks X 16 bits
  • Refresh every 64ms
  • Supports pipelining
  • Bidirectional data lines

42
DDR DRAM
  • Double Data Rate SDRAM
  • Transfers data on both edges of the clock
  • Currently popular
  • Attempt to alleviate the pinout problems

43
RAMBUS DRAM (RDRAM)
  • Another attempt to alleviate pinout limits
  • Many (16-32) banks per chip
  • Made to be read/written in packets
  • Up to 400MHz bus speeds
  • But DDR doing very well also

44
DRAM Controllers
  • Very common to have chip that controls memory
  • Handles banks
  • Handles refresh
  • Multiplexes column and row addresses
  • RAS and CAS timing
  • Northbridge on PC chip set

45
Today
  • Learned all about RAM
  • Static RAM
  • Simple, small, expensive
  • Fast, used for cache
  • Dynamic RAM
  • Complex, largest, cheap
  • Needs periodic refresh

46
Links
  • Ram Guides (not very technical)
  • http//arstechnica.com/paedia/storage.html
  • DRAM on XSA-100 board
  • http//www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V
    281620A(L)T-I.PDF

47
Next Time
  • Nonvolatile memories
  • Programmable logic
  • Whats inside our FPGA
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