AGATA Digitiser Summary February 2005

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AGATA Digitiser Summary February 2005

• Patrick J. Coleman-Smith
• For the Digitiser Technical Group

• I.Lazarus Daresbury
• P.Medina IReS
• R.Baumann IReS
• C.Santos IReS
• M.Chambit IReS
• J.Thornhill Liverpool
• D.Wells Liverpool

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• Revised Mechanical Structure
• Global Clock internal delivery
• Laser link trial report
• TNT2 tests
• Slow Control
• Cost
• Schedule
• Some Remaining Questions

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Previous Mechanical Structure
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New Mechanical Assembly

• Mechanical Constraints
• Distance to the Detector 5 Metres
• Power Dissipation around 400W
• Mechanically dependant on the detector array.
• Use Water Cooling

New arrangement of PCBs
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Structure of the Digitiser Cooling, and mechanics
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Internal Global Clock Distribution

• Clock reference input from the Pre-Processor core
  board using Laser link.
• The idea is to use Sinusoidal clock through a
  Jitter smoother and a Mini-circuit splitter
• Distribute to the Flash ADCs via cable.
• Passive Filter to transform the square wave input
  to a sinusoidal signal

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Internal Global Clock distribution
schematicUnder Development at Liverpool
University
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Laser Trial Test and Results

• Designed the Laser Trial board with four Laser
  modules.
• Used Xilinx recommended PCB connection parameters
  for the 2Gbit/sec connections from the Virtex2Pro
  BGA to the Laser modules.
• Test connection to a Xilinx Development board
• 16 bit data from counter incrementing at 100Mhz
• Three channels operating independently.
• Receiver tracks the data, checking each value
  received.
• Transmitter and receiver share the same clock.
• Ran for 8 days with no errors.
• 6.9 x 1013 Transfers per link

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Laser Trial Test Block Diagram
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Laser Trial Board
Laser Transmitter
Analog Inspection
Virtex2Pro
100Mhz clock input
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Laser Trial Setup
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TNT2 Tests 1
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TNT2 Tests 2
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Slow Control

• External interfaces Xport module
• Galvanically isolated serial link over
  10/100baseT physical layer.
• Experiment control for the digitiser.
• Laboratory and diagnostic access.
• Internal interfaces Serial link
• Link is Clock, Data, Frame signals
• Simple protocol developed at Liverpool.
• Connects all FPGAs using Star topology.
• Requests all generate an Acknowledge.
• Timeout with reset of link.
• Long write to allow re-program of FPGA.

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Cost Estimates
Prototype Digitiser 45,000 Euros Further
Digitisers 30,000 Euros  
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Schedule
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Some Remaining Questions

• Offset Control link protocol
• Segment and Core data link start-up protocol,
  and how to respond to failures.
• Global clock link start-up and calibration
• Pre-Amp Interface - Pulser Control
• Slow Control External interface protocol
• Mechanical mounting on the Apparatus

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Signal interconnections
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Front panel clock interconnects
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Main Structure of the digitiser housing
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Block Diagram of the Digitiser
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Segment board block diagram
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DC-DC graphs
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Clock Test boards
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Slow control test board