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Computer Architecture and the Fetch-Execute Cycle

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Title: Computer Architecture and the Fetch-Execute Cycle


1
Computer Architecture and the Fetch-Execute Cycle
  • Memory Addressing Techniques

2
Learning Objectives
  • Explain the concepts of direct, indirect, indexed
    and relative addressing of memory when referring
    to low-level languages.

3
Memory Addressing Techniques
  • Direct Addressing
  • Indirect Addressing
  • Indexed Addressing
  • Relative Addressing
  • Immediate Addressing

4
Direct Addressing
5
Direct Addressing
  • Means that the value in the address part of a
    machine code instruction is the address of the
    data.
  • Simple to use but does not allow access to all
    memory addresses as there are memory addresses
    larger than can be held in the address part of an
    instruction.
  • e.g. A 32-bit memory location may use 12 bits for
    the instruction code and 20 bits for the address
    of the data.
  • This would allow for 212 ( 4096) instruction
    codes and 220 ( 1 048 576) memory addresses.
  • However, a computer using 32-bit memory locations
    will have 232 ( 4 294 967 296) memory
    addresses.
  • So direct addressing does not allow reference to
    all addresses e.g. for a computer using 32-bit
    memory locations, addresses from 220 232
    cannot be referred to.

6
2. Indirect Addressing
7
Indirect Addressing
  • Means that the value in the address part of a
    machine code instruction is the address of the
    address of the data.

8
Why use indirect addressing?
  • Allows more memory to be accessed than direct
    addressing as the full size of register is used
    for an address.
  • If this value points to a location which holds
    nothing but an address then 232 locations in
    memory can be addressed.

9
3. Indexed Addressing
10
Indexed Addressing
  • Index Register (IR)
  • A special register used to adjust the address
    part of an instruction in the CIR.
  • The original address part of the instruction in
    the CIR is now changed by adding the contents of
    the index register (IR) to it, to give an new
    effective address of the data.

11
Indexed Addressing can be used once during one
Fetch-Decode-Execute-Reset Cycle
  • To reach a particular element in an array or
    field in a record.
  • IR Offset of the required element or field from
    the start of the array or record.
  • Instruction address Address of the start of the
    array or record.

12
Indexed Addressingcan be used repeatedly
  • To allow a number of fields in contiguous records
    or contiguous elements in an array to be accessed
    by incrementing the Index Register (IR) between
    each successive access instruction.

13
Why use Indexed Addressing?
  • Why not do something similar to the high-level
    instruction?
  • Address Address Offset
  • Add NewAddress
  • Doing it this way would involve
  • Reserving two memory addresses
  • Address Offset.
  • 8 Fetch-Decode-Execute-Reset cycles
  • Set the address, set the Offset, load Address,
    add Offset, store the new address, access the
    contents of this indirect address, load offset,
    check if offset is lt or gt than a specified
    condition otherwise loop back.

14
Why use Indexed Addressing?
  • Indexed addressing avoids this
  • Note that it is usual decrement instead of
    increment as most computers have a command to
    test if a register is below 0, which provides a
    convenient method of stopping the loop.
  • Set the IR No of elements required-1
  • Access (Address of 1st element IR)
  • Decrement IR by 1
  • Test if IR lt 0 otherwise loop back to step 2.
  • This only involves only 4 Fetch-Decode-Execute-Res
    et cycles and one register (IR).
  • Note the IR is in the processor, not memory so no
    memory locations are used in indexed addressing.

15
Indexed Addressing
e.g. to add 5 memory locations
- 1
16
Indexed Addressing
17
Indexed Addressing
18
Indexed Addressing
19
Indexed Addressing
STOP
20
Why use Indexed Addressing?
  • This means that the original access instruction
    as written in the code does not need to be
    modified .
  • Also avoids 4 additional cycles and using 2
    memory locations.
  • Note the IR is in the processor, not memory so no
    memory locations are used in indexed addressing).

21
Why use Indexed Addressing?
  • Note for fields in a record then
  • Set the IR No of records required - 1
  • Address in access instructionAddress of 1st
    record
  • Decrement IR by offset.

22
For more research
  • http//www.docstoc.com/docs/21677063/INSTRUCTION-A
    DDRESSING-MODES

23
4. Relative Addressing
24
Relative Addressing
  • Address in the instruction is the displacement
    from the current instructions address 1 (due
    to the PC being incremented) already in the PC.
  • Used mainly with jump instructions.
  • The address in the instruction is added to the
    value in the PC.
  • e.g.
  • The current instruction is in address 3000 and is
    Jump 45, using relative addressing this means
    that the line wants to jump to an instruction 45
    lines ahead of the next instruction (due to the
    PC being automatically incremented by 1 during
    any Fetch-Decode-Execute-Reset Cycle this means
    46 lines ahead of the current instruction).
  • The PC will have been incremented to 3001 (ready
    for the next instruction) so the PC is changed to
    300145 3046.
  • The next cycle retrieves the next instruction
    from there.
  • The program knows where the line is relative to
    the current instruction but not the true address
    see Memory Management Presentation or next 2
    slides.

25
Index Table
Displacement e.g. 45
Physical Address e.g. 300145 3046
26
Physical Address e.g. 35011313632
Displacement e.g. 131
Segment Index Table
27
Relative Addressing
  • Can also be used to access data in addresses
    relative to the current instruction.
  • The only difference is that the new effective
    address would be loaded into the MAR instead of
    the CIR.

28
Relative Vs Indexed Addressing
  • Similar as they both involve changing an address
    by addition but
  • Indexed Addressing
  • Changes the address in the instruction in the
    CIR.
  • Address limited to the size of the address field
    in the CIR, as in direct addressing.
  • Effective address address in the CIR contents
    of IR
  • Relative Addressing
  • Changes the address in the PC or MAR not the
    address in the instruction in the CIR.
  • Address can be full value of the register as
    modified effective address is on its own in the
    PC or MAR.
  • Effective address current instructions address
    1
  • value in
    instruction

29
For more research
  • http//www.edsim51.com/8051Notes/8051/instructionS
    etSummary.html
  • http//en.wikipedia.org/wiki/Addressing_modes

30
5. Immediate Addressing
31
Immediate Addressing
  • Immediate addressing is so-named because the
    value to be stored in memory immediately follows
    the operation code in memory.
  • e.g. Load 20 where 20 refers to a value and is
    loaded directly into the accumulator.
  • You could argue that there is no address being
    used at all, but there you go!
  • Immediate addressing is very fast since the value
    to be loaded is included in the instruction.
  • However, since the value to be loaded is fixed at
    compile-time it is not very flexible.

32
Immediate Addressing
  • Advantage
  • No memory reference other than instruction fetch
    is required to obtain the data to be used.
  • Disadvantage
  • The size of the number is limited to the size of
    the address field, which most instruction sets is
    small compared to word length.
  • This is the similar to the problem direct
    addressing has.

33
For more research
  • http//www.edsim51.com/8051Notes/8051/instructionS
    etSummary.html
  • http//www.docstoc.com/docs/21677063/INSTRUCTION-A
    DDRESSING-MODES

34
Plenary
  • State the 4 methods of memory addressing and
    explain why they are used.
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