Heterogeneous Computing with Nanoscale Architectures for Bio Applications Mary Mehrnoosh EshaghianWi

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Heterogeneous Computing with Nanoscale
Architectures for Bio Applications Mary
Mehrnoosh Eshaghian-WilnerAdjunct Professor of
Electrical EngineeringUniversity of California,
Los Angeleswww.seas.ucla.edu/eshaghia
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Outline of this talk

• Three levels of Heterogeneous Computing
• Network
• System
• Architecture
• Heterogeneous Computing with Cluster-M
• Architecture Heterogeneous Computing
• Spin-Wave Architectures
• Fully Connected Cluster
• Crossbar
• Reconfigurable Mesh
• Bio Applications
• Future Research

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What is Heterogeneous Computing?

• Heterogeneous computing is a special form of
  parallel and distributed computing that could be
  applied to different levels of a computing
  organization.
• In the 1996 Heterogeneous Computing book, two
  levels were described
• Network level (Network Heterogeneous Computing)
• System level (System Heterogeneous Computing)
• Here, we discuss a third level to which
  heterogeneous computing can also be applied
• Architecture level (Architecture Heterogeneous
  Computing)

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In Network Heterogeneous Computing (also known as
Grid/Cluster/wide-area Computing), computations
are done using a geographically distributed set
of connected autonomous computers
http//www.cybergeography.org/atlas/geographic.htm
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http//www.planetary.org/solarsail/spacecraft_desi
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System Heterogeneous Computing

• Mixed-Mode
• SIMD or MIMD Concurrently
• Example PASM
• Multi-Mode
• SIMD and MIMD Simultaneously
• Example The IUA model
• A newer Example
• The Cell Processor (8 SIMD cores and 1MIMD core
  Similar to G5)

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Architecture Heterogeneous Computing

• In Architecture Heterogeneous Computing,
  diversity is in terms of the underlying
  technologies that are used at the chip level.
• For example, we are concerned with the types of
  chips that may be multi-scale containing
• both Nano and MEMS components,
• and/or may use both analog and digital,
• and/or may employ both electrical and optical
  interconnects,
• and/or may use both classical and quantum
  computations.

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Suitable Abstract Model of Computation for
Heterogeneous Computing

• PRAM (Homogeneous)
• Shared Memory Unit time access
• Local Memory PRAM (Homogeneous)
• Distributed Memory Unit time access
• Log-P (Homogeneous)
• Need to know Processor counts
• Average distance
• Unloaded communication time
• Latency
• Communication overhead
• Cluster-M (Heterogeneous)
• Programming totally independent of machine

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Cluster-M Model
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Mapping with Cluster-M

• Mapping of a set of arbitrary tasks onto a
  arbitrary system

P1
Cluster-M MappingTool and Algorithm
P2
P3
PN
Tasks
Processor NodesHeterogeneous
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How is the Clustering done in Cluster-M?

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The Cluster-M Clustering of Task Graphs, for
Joint-Nodes



.
.
.
.
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The Cluster-M Clustering of Task Graphs, for Fork
Nodes

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Example The Cluster-M clustering of Task graphs
Figure 1
Figure 3
Figure 2
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Clustering System Graphs
A System Graph is always undirected.
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Mapping of the Clusters

• Or nodes are embedded if the overhead threshold
  is exceeded

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Example of Cluster-M mapping
Gantt chart of the obtained schedule.
A mapping example
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The Time complexity of Cluster-M

• O(KiN) time to find the best matches for all Ki
  Spec clusters.
• The total number of Spec cluster is O(M).
• The total time complexity

, where N M.
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Architecture Heterogeneous Computing

• Architectures with different technologies
• Optoelectronics, Spintronics
• Analog vs. Digital
• Classical vs. Quantum
• MEMS/Nano

Intel Silicon Laser
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Architecture Heterogeneous Computing with
Nanoscale Devices
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Some of the Current Developments

• Switching Devices
• Resonance Tunneling Devices
• Quantum Dots
• Single-Electron Transistors
• Other molecular electronic devices
• Superconductivity
• Single-walled carbon nano-tube (SWNT)
• Quantum Computing
• DNA Computer
• Spintronics
• Information is stored into spins as a spin
  orientation Spins carriers are transferred
  through conducting wires
• Charge Transfer ? High Power Consumption
• Interconnectivity issue ?Still have wires

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A New Approach Wave-based SpintronicsAlex
Khitun and Kang Wang, 2005The spin waves are
used as a communication medium- The phase of the
waves are used for information processing
Input Pulse 24.5V Rising time 1.2ns Pulse
length 20ns
Output Max. pulse 26mV period 9ns
Cobalt Iron - Device Prototype with Asymetric
Coplanar Stips- Signal to noise ratio
satisfactory for 8micrometer. Energy per spin
wave several KT just above thermal noise level
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What is a Spin Wave ?

• Electron Spin produces a Magnetic Moment.
• If a magnetic field is applied, the spin moment
  will precess about the field.
• A collection of such spin precessions is a spin
  wave
• Speed is 100,000 m/s, GHz switching
• Attenuation 50 Microns

Image from Mingzhong Wu et al., Colorado State
University
A collection of spin precessions Image by Alex
Khitun
Information obtained from Slides prepared by
Mingzhong Wu, Carl E. Patton, and Boris A.
Kalinikos Department of Physics, Colorado State
University, Fort Collins, Colorado
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Properties of Spin Wave in Algorithm Design

• Information can sent at multiple frequencies
• Information can be combined using superposition
• Information can be encoded in both digital and
  analog domain

Image from Mingzhong Wu etc. al. Department of
Physics, Colorado State University, Fort Collins,
Colorado
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Logic Functionality (Numerical Simulations)
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Towards the Design of an Ideal Chip

• High utilization of area
• O(N) Processors in O(N) area?
• Low intercommunication delay
• O(1) diameter?
• Implementable
• Unbounded Fan-in Fan-out nodes?
• Nanoscale level of integration
• Power efficient?

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Limitations with Design of Fully Connected
Networks in VLSI

• Area-time tradeoff Limitation
• AT2?(I)2
• Limited Fan-in/Fan-out,
• O(1) degree communication with N nodes not
  possible, ?(log(N)) delay

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Computational Limits of Nano structures

• For Nano, VT3/2?(I)3/2, as compared to VLSI,
  AT2 ?(I)2

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Our Proposed Architectures using Spin Waves

• No point-to-point physical connection needed
• Area efficient chips with high level of
  utilization
• No multiple Fan-in Fan-out problems
• Waves can pass through each other
• No layout problems for the wires
• Multiple waves at different frequencies
• Power efficient
• No charge is transferred
• Information coded in the phase of the spin wave
• Both digital and analog computations can be done
• Operatable at room temperature
• Implementable at nano scale level

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Spin-Wave Architectures

• Fully Interconnected Cluster
• Crossbar
• Reconfigurable Mesh
• Hierarchical Architectures
• Integration of Spin-Wave Modules with MEMS
• Hierarchical Multi-scale Fully Interconnected
  Clusters
• Hierarchical Multi-scale Crossbar
• Hierarchical Multi-scale Reconfigurable Mesh

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A Fully Interconnected Network

• All nodes are interconnected
• The receiver node can detect the message if it is
  sent on the frequency it is tuned on

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A Nano-scale Module with Full Spin-Wave
Interconnectivity for Integrated Circuits
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Hierarchical Multi-scale Fully interconnected
Cluster
ORMs Optical Interconnection
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ORM Micro-Mirrors
ORM Switch
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ORM Optical Routing

• Uses reconfigurable MEMS switches
• Through free space interconnections

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Spin-Wave Crossbar Architecture
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Implementation of the Nanoscale Crossbar with
Spin-wave Buses
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• DMS cell transmit spin waves in ferromagnetic
  state- negative bias increases the hole
  concentration
• No transmission in paramagnetic state- positive
  bias decreases the hole concentration in diluted
  magnetic semiconductor (DMS) switch

H. Ohno, Making Nonmagnetic Semiconductors
Ferromagnetic, SCIENCE, V281, (1998).
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Hierarchical Multi-scale Crossbar
ORMs Electro-Optical Interconnection
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ORM Electro-Optical Routing

• Uses fixed MEMS mirrors
• Switching time of nano-second
• In EREW, any PE P(i,i) sends data to P(k,k) in
  the following way
• First, P(i,i) sends the data to P(i,k) through
  the electrical row bus
• Then, P(i,k) sends data to P(k,k) using its
  deflector M(i,k).

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Spin-Wave Reconfigurable Mesh
Figures obtained from Slides prepared by Heiko
Schröder, 1998
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Spin-wave Reconfigurable Switches
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Hierarchical Multi-scale Reconfigurable Mesh
ORMs Electrical Interconnection
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ORM Electrical Routing

• Uses electrical buses and switches
• Standard reconfigurable mesh
• Switching time of nano-second

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Sequence alignment on Spin-Wave Reconfigurable
Mesh An example of Architecture Heterogeneous
Computing
The similarities amongst the sequences are now
extracted.
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Expanding the scale

• Let us expand the scale of the sequences
• Example of an alignment of larger sequences

Imagine if we had many more of them Imagine if
we had gene sequence data
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Partial Order Alignment 1

• Chris Lee describes a way to use directed acyclic
  graphs to represent aligned sequence data.
• The resulting graph representation is denoted
• Partial Order Multiple Sequence Alignment Graph /
  Representation (PO-MSAG)

Chris Lee. MSA using Partial Order Graph, 2002
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Graph forming using the Graph Column
Graph Column

• Shift the active nodes to the right slot.
• Move the repeated nodes to the slots underneath
  the active node.

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Transmission of Spin Waves at Different
Frequencies
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The Superposition of Spin Waves
Digital Computation Output 1 Analog
Computation Output 5
Same Frequency
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Node Elimination

• We close all switches in the channel, with a
  10-14 s delay between each consecutive nodes.
• At around 10-9 s, we transmit the a signal at the
  first node.
• After 10-14 s, the first wave propagate to the
  next node, and the switch is closed.
• The next node will transmit another signal.

• Why is it constant?
• To reach the end of the channel, it will take as
  much time as we send a signal from node 1 to the
  end, and we define that time as our constant
  time.

Amplitude 1
Amplitude 1
Amplitude 2
Amplitude 3
Amplitude 4
Transmitter/ Receiver
Switch
Bottom
Top
G
A
A
A
A
Receives a signal in Frequency A
Receives a signal in Frequency A
Receives a signal in Frequency A
Channel
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Output and Complexity
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Graph Databases

• Motivation
• To organize highly relational graph databases
• Example ABCDEG ABCDFG

Typical Databases
At the UCLA Bioinformatics Program, Prof. D.S.
Parker, and Prof. C. Lee, are working on Graph
Databases
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Cluster-M for Bio-informatics
Cluster-M Mapping Algorithm
Data in Partial Order Graph 1
Data in Partial Order Graph 2
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More on the Cluster-M process
Sequence 2
Sequence 1
Level 2
Level 1
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Examples of Graphs for Cluster-M
2
1
10
0
3
1
2
2
1
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Result ComparisonCluster-M Vs. El-Rewini and
Lewis mapping heuristic
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Designing Application Algorithms
Biologically inspired image computations

• Mapping of massively parallel image computations
• Concurrent Write possible

Modeling Neural Networks E.g. Hopfield Model
Convex Hull
Background http//groups.csail.mit.edu/vision/med
ical-vision/surgery/surgical_navigation.html
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Other Future Research Implantable Bio-medical
Nano-scale Devices
Nano scale devices
Health Problem Detection
Body http//www.kentleech.com/humanbody.html
Blood vessel http//www.erc-assoc.org/showcase/ac
complishments/microelectronic/wims-05-6-activesten
t.htm
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Some of Our 2006 Papers on Spin-Wave Architectures

• 1- A Nanoscale Module with Full Spin-Wave
  Interconnectivity for Integrated Circuits, Mary
  M. Eshaghian-Wilner, Alex Khitun, Shiva Navab and
  Kang Wang, NSTI Nanotech 2006, Boston, May 7-11,
  2006.
• 2- A Nanoscale Reconfigurable Mesh with Spin
  Waves, Mary M. Eshaghian-Wilner, Alex Khitun,
  Shiva Navab, and Kang Wang, the ACM International
  Conference on Computing Frontiers, Italy, May
  3-5, 2006.
• 3- Graph Formations of Partial-Order
  Multiple-Sequence Alignment using Nano- and
  Micro-scale Reconfigurable Meshes," Mary M.
  Eshaghian-Wilner, Jonathan Lau, Shiva Navab, and
  David Shen, accepted for publication at the 2006
  International Conference on Computing in
  Nanotechnology, to be held in Las Vegas, USA,
  June 26-29, 2006.
• 4- Hierarchical Multi-Scale Architectures with
  Spin Waves, Mary M. Eshaghian-Wilner, Alex
  Khitun, Shiva Navab, and Kang Wang, accepted for
  publication at the 2006 International Conference
  on Computing in Nanotechnology, to be held in Las
  Vegas, USA, June 26-29, 2006.
• 5- A Nanoscale Crossbar with a Spin Waves ,
  Mary M. Eshaghian-Wilner, Alex Khitun, Shiva
  Navab, and Kang Wang, accepted to the 6th IEEE
  Conference on Nanotechnology, to be held in Ohio,
  USA, July 16-20, 2006.
• 6- Nanoscale Reconfigurable chips for Image
  Processing, Mary M. Eshaghian-Wilner, Alex
  Khitun, Shiva Navab, and Kang Wang, in
  preparation for submission to in preparation for
  submission to the Trends in Nanotechnology
  Conference, to be held in France, September, 4-8,
  2006.
• 7- Implementing Neural Networks in Nanoscale,
  with Alex Khitun, Shiva Navab, and Kang Wang, in
  preparation for submission to the International
  Conference on Nano Science and Technology, to be
  held in Switzerland, July 30-August 4, 2006.
• 8- Nano-scale modules with full spin-wave
  interconnectivity, with Alex Khitun, Shiva Navab
  and Kang Wang, to appear in a special issue of
  Journal of Experimental Nanoscience, 2006-2007.
• 9- The Spin-wave Reconfigurable Mesh, with Alex
  Khitun, Shiva Navab and Kang Wang, recommended
  for inclusion at a special issue of the ACM
  Transaction on Emerging Technology, 2006-2007.
• 10- "Image Processing on Spin-wave
  Nano-architectures," with Alex Khitun, Shiva
  Navab and Kang Wang, to appear in a special issue
  of the "physica status solidi" (a) Journal,
  2006-2007.
• 11- Implementing Neural Networks in Nanoscale,
  with Aaron Friesz, Alex Khitun, Shiva Navab,
  Alice C. Parker and Kang Wang, to appear in a
  special issue of the Journal of Physics
  Conference Series, 2006-2007.
• 12- Parallel Graph Formations of Partial-Order
  Multiple-Sequence Alignments Using Nano-, Micro-,
  and Multi-Scale Reconfigurable Meshes, submitted
  to the IEEE/ACM Transaction on Computational
  Biology and Bioinformatics, 2006.

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Current Collaborators at EE-UCLA Dr. Alex
KhitunDr. Kang Wang Current UCLA Students
Ms. Shiva Navab
Mr. Ling (Jonathan) Lau
Mr. David Shen
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• Visit us at http//www.seas.ucla.edu/eshaghia/lab
  _web

Thank you