MultiFrequency Wrapper Design and Optimization for Embedded Cores under Average Power Constraints

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Multi-Frequency Wrapper Design and Optimization
for Embedded Cores under Average Power
Constraints
Qiang Xu, Nicola Nicolici McMaster
University Krishnendu Chakrabarty Duke
University
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Outline

• Research Problem Overview
• Multi-Frequency Wrapper Design
• Multi-Frequency Wrapper Optimization
• Experimental Results
• Summary

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SOC with Multiple Clock Domains
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Scan Design with Multiple Clock Domains
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Clock Skew during Shift

• Having separate scan chains for each clock domain
• Using level-sensitive scan design (LSSD) scan
  cells
• Grouping flip-flops (FFs) from the same clock
  domain and adding lockup- latches between
  different clock domains

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Clock Skew during Capture

• Mask potential hazards using control and/or
  observe points
• Capture window design ATPG techniques

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Capture Window Design to Avoid Skew

• Combinational ATPG
• High test pattern count

Source http//www.mentor.com/dft/techpapers/
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Capture Window Design to Avoid Skew

• Sequential ATPG
• Low test pattern count

Source http//www.mentor.com/dft/techpapers/
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At-speed Testing

• Launch/Capture at rated-speed
• Scan shifting can be at slower frequency
• Helps to detect timing-related defects

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IEEE Std. 1500 Core Test Wrapper
Source Marinissen et al. ITC2000
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Multi-Frequency Wrapper Design
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Previous Scan Control Block Design
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New Scan Control Block Design
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Previous Timing Diagram
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New Timing Diagram
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Multi-Frequency Wrapper Optimization
- Problem Definition

• Given test set parameters
• Number of clock domains Nc
• Ni, No, Nbi, Nsc, SClength, Pi, Nv, for each
  clock domain i
• Average test power constraint Pave
• ATE shift frequency ft
• External TAM width Wext
• Determine the wrapper design
• Shift frequency fsi, VTB lines width Wi for each
  clock domain i
• Wrapper scan chain design

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Multi-Frequency Wrapper Optimization
- ILP Formulation

• Suppose the possible shift frequencies for each
  VC are
• which satisfy
• Classical min-max ILP formulation
• Complexity
• Number of Variables
• Number of Constraints

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Multi-Frequency Wrapper Optimization
- Fast Heuristic

• Initially assume all VTB lines shifting at FM
• Assign one VTB line to each virtual core
• Wrapper scan chain design for each
  single-frequency VC
• Repeat
• Assign one VTB line to the virtual core with the
  maximum shifting time
• Select the fs/NVTB that minimizes its overall
  test cost, which considers both shifting time and
  test power consumption

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Experimental Results Core Config.
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Experimental Results
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Experimental Results
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Summary

• Wrapper Design for Multi-Frequency Cores
• 1500-Compliant
• Avoid clock skew during test
• Allow different VCs operate at different
  frequencies
• Wrapper Optimization tradeoff
• Testing time
• Routing overhead
• Average power dissipation