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Logic Gates

- Logic gates are electronic digital circuit

perform logic functions. Commonly expected logic

functions are already having the corresponding

logic circuits in Integrated Circuit (I.C.) form.

Design of Circuit Procedures

- Obtain a precise circuit specification
- Development of a truth table
- Identifying the minterms corresponding to each

row in the table. - Drawing Karnaugh maps
- Forming groups of 1s on the Karnough map
- Writing the reduced expression
- Converting the reduced expression into a

realizable expression - Drawing the circuit diagram
- Construct and test a prototype circuit.

Types of Logic Gates

Basic Gates

AND , OR , NOT

AND Gate

- The AND gate implements the Boolean AND function

where the output only is logical 1 when all

inputs are logical 1. - The standard symbol and the truth tabel for a two

input AND gate is

Boolean expression of AND

- The Boolean expression for the
- AND gate is RA.B

OR Gate

- The OR gate implements the Boolean OR function

where the output is logical 1 when just input is

logical 1. - The standard symbol and the truth table for a two

input OR gate is

Boolean Expression of OR

The Boolean expression for the OR gate is RAB

NOT Gate

- The NOT gate implements the Boolean NOT function

where the output is the inverse of the input. - The standard symbol and the truth table for the

NOT gate is

Boolean Expression of NOT

- The Boolean expression for the NOT gate is R-A

Derived Gates

- NAND , NOR , XOR

NAND Gate

- The NAND gate is an AND gate followed by a NOT

gate. The output is logical 1 when one of the

inputs are logical 0 - The standard symbol and the truth table for the

NAND gate is

Boolean expression of NAND

NOR Gate

- The NOR is a combination of an OR followed by a

NOT gate. The output is logical 1 when non of the

inputs are logical 0 - The standard symbol and the truth table for the

NOR gate is

Boolean Expression of NOR

XOR Gate

- The XOR gate produces a logic 1 output only if

its two inputs are different. If the inputs are

the same, the output is a logic 0 - The XOR symbol is a variation on the standard OR

symbol. It consists of a plus () sign with a

circle around it. The logic symbol, as shown

here, is a variation on the standard OR symbol.

Exercise 1

- http//kom.auc.dk/logic/

De-Morgans Theorem and Logic Conversion

- 1)
- 2)
- 3)
- 4)

Implement the logic expression using NAND gates

only

1)

2)

Implement logic expression using NOR gates only

1)

Revision Exercise

- http//www.nottingham.ac.uk/cczwood/TestCourses/l

ogic/logic-intro.html - http//www.cs.odu.edu/jbollen/CS149/demos.html
- http//sandbox.mc.edu/bennet/cs110/boolalg/gate.h

tml - http//www.cs.stedwards.edu/jsnowde/start.htm

Combinational Logic Designs

- A combinational logic circuit can be described by

the block schematic shown - Each output is a function of some or all of the

input variables, Hence - O1f(I1,I2,....,In) O2f(I1,I2,,In) ...
- and Onf(I1,I2,,In)

I1

O1

Combinational Logic

In

On

Half Adder

What is a Half adder

- Logic gate that perform addition for 1-bit
- When 1 1 occurs, a carry produce 1

Half Adder

- Perform arithmetic additions
- two inputs A, B to half-adder. Resultants are

Sum(S) and Carry(Cout) - Using K-Map to simplify the sum term, we get

A

S

H.A

B

Cout

Full Adder

What is Full Adder

- A full adder is a circuit that computes the sum

of three bits and gives a two-bit answer. - A circuit for adding two 16-bit numbers can be

built from 16 full-adder circuits. Each

full-adder does one column of the sum. - The full adder for a given column adds two bits

from the input numbers together with a one-bit

carry from the previous column to the right. The

adder produces a two-bit answer one of these

bits is used as a carry into the next column.

Full Adder

- A full adder has 3 inputs and 2 outputs
- The truth table of the full-adder can be
- drawn with inputs A,B and Cin with outputs S and

Cout - From the truth table we can write the Boolean

equation for the S and Cout - Simplify using Boolean Algebra and K-map, we get

Sum Any 2 of the three inputs are 1Cout XOR

between A, B, Cin

Full Adder diagram

Half Subtractor

What is a Half Subtractor

- A logic gate that perform 1 bit subtraction
- When 0-1 occurs, a carry produces 1

Half Subtractor

C

A

B

D

0

0

0

1

0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

2

1

0 -1 1

Half Subtractor

- Operation A - B

Full Subtractor

What is a Full Subtraction

- Logic gates that perform two bits subtraction

Full Subtractor

Ci Ai Bi Di Ci1

0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1

0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1

1

1

1

1

Di

Full Subtractor

Ci Ai Bi Di Ci1

0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1

0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1

1

1

1

1

Ci1

Ci1 !Ai Bi Ci !Ai !Bi Ci

Ai Bi

Full Subtractor

Ci1 !Ai Bi Ci !Ai !Bi Ci

Ai Bi

Ci1 !Ai Bi Ci (!Ai !Bi Ai

Bi) Ci1 !Ai Bi Ci !(Ai Bi)

Recall

Di Ci (Ai Bi)

Ci1 !Ai Bi Ci !(Ai Bi)

Full Subtractor

Di Ci (Ai Bi)

Ci1 !Ai Bi Ci !(Ai Bi)

Full Subtractor

- Operation A - B - Bin

Adder/Subtractor - 1

Half subtractor

Half adder

E 0 Half adder

E 1 Half subtractor

Adder/Subtractor-1

i1

E 0 Full adder E 1 Full subtractor

Reordered Full Adder

Full Adder

Ci Ai Bi Si Ci1

Ci Ai Bi Si Ci1

0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1

0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0

0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0

NOT

Making a full subtractor from a full adder

Four-Bit Parallel Adder

- This circuit is sometimes referred to as a

ripple-through adder - C0 ripples through four two-level logic circuits

and hence the sum cannot be completed until eight

gate delays - For this kind of adder, the maximum delay is

directly proportional to the number of stages n.

Adder/Subtractor-2

E 0 4-bit adder E 1 4-bit subtractor

Carry Look-Ahead Circuit

- To improve the speed of addition
- Consider the carry output equation for a full

adder is - Which can be expressed as follows
- or as
- where

Carry Look-Ahead Circuit

- Four a four-bit adder the generate and propagate

terms for each stage are - while the carries for the various stages are

Carry Look-Ahead Circuit

- Substituting for C0 in the C1 equation etc leads

to the following equations - And the sum
- Since the number of levels of logic required when

a large number of bits has to be added does not

increase then the Carry Look-Ahead adder will

provide a faster addition time

Binary Multiplication

- Paper and Pen method
- which is implemented using
- 9 AND gates, 3 FA and
- 3 HA

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