Logic Gates

1
Logic Gates

• Logic gates are electronic digital circuit
  perform logic functions. Commonly expected logic
  functions are already having the corresponding
  logic circuits in Integrated Circuit (I.C.) form.

2
Design of Circuit Procedures

• Obtain a precise circuit specification
• Development of a truth table
• Identifying the minterms corresponding to each
  row in the table.
• Drawing Karnaugh maps
• Forming groups of 1s on the Karnough map
• Writing the reduced expression
• Converting the reduced expression into a
  realizable expression
• Drawing the circuit diagram
• Construct and test a prototype circuit.

3
Types of Logic Gates
4
Basic Gates
AND OR NOT
5
AND Gate

• The AND gate implements the Boolean AND function
  where the output only is logical 1 when all
  inputs are logical 1.
• The standard symbol and the truth tabel for a two
  input AND gate is

6
Boolean expression of AND

• The Boolean expression for the
• AND gate is RA.B

7
OR Gate

• The OR gate implements the Boolean OR function
  where the output is logical 1 when just input is
  logical 1.
• The standard symbol and the truth table for a two
  input OR gate is

8
Boolean Expression of OR
The Boolean expression for the OR gate is RAB
9
NOT Gate

• The NOT gate implements the Boolean NOT function
  where the output is the inverse of the input.
• The standard symbol and the truth table for the
  NOT gate is

10
Boolean Expression of NOT

• The Boolean expression for the NOT gate is R-A

11
Derived Gates

• NAND NOR XOR

12
NAND Gate

• The NAND gate is an AND gate followed by a NOT
  gate. The output is logical 1 when one of the
  inputs are logical 0
• The standard symbol and the truth table for the
  NAND gate is

13
Boolean expression of NAND
14
NOR Gate

• The NOR is a combination of an OR followed by a
  NOT gate. The output is logical 1 when non of the
  inputs are logical 0
• The standard symbol and the truth table for the
  NOR gate is

15
Boolean Expression of NOR
16
XOR Gate

• The XOR gate produces a logic 1 output only if
  its two inputs are different. If the inputs are
  the same the output is a logic 0
• The XOR symbol is a variation on the standard OR
  symbol. It consists of a plus () sign with a
  circle around it. The logic symbol as shown
  here is a variation on the standard OR symbol.

17
Exercise 1

• http//kom.auc.dk/logic/

18
De-Morgans Theorem and Logic Conversion

• 1)
• 2)
• 3)
• 4)

19
Implement the logic expression using NAND gates
only
1)
2)
20
Implement logic expression using NOR gates only
1)
21
Revision Exercise

• http//www.nottingham.ac.uk/cczwood/TestCourses/l
  ogic/logic-intro.html
• http//www.cs.odu.edu/jbollen/CS149/demos.html
• http//sandbox.mc.edu/bennet/cs110/boolalg/gate.h
  tml
• http//www.cs.stedwards.edu/jsnowde/start.htm

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Combinational Logic Designs

• A combinational logic circuit can be described by
  the block schematic shown
• Each output is a function of some or all of the
  input variables Hence
• O1f(I1I2....In) O2f(I1I2In) ...
• and Onf(I1I2In)

I1
O1


Combinational Logic
In
On
23
Half Adder
24
What is a Half adder

• Logic gate that perform addition for 1-bit
• When 1 1 occurs a carry produce 1

25
Half Adder

• Perform arithmetic additions
• two inputs A B to half-adder. Resultants are
  Sum(S) and Carry(Cout)
• Using K-Map to simplify the sum term we get

A
S
H.A
B
Cout
26
Full Adder
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What is Full Adder

• A full adder is a circuit that computes the sum
  of three bits and gives a two-bit answer.
• A circuit for adding two 16-bit numbers can be
  built from 16 full-adder circuits. Each
  full-adder does one column of the sum.
• The full adder for a given column adds two bits
  from the input numbers together with a one-bit
  carry from the previous column to the right. The
  adder produces a two-bit answer one of these
  bits is used as a carry into the next column.

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Full Adder

• A full adder has 3 inputs and 2 outputs
• The truth table of the full-adder can be
• drawn with inputs AB and Cin with outputs S and
  Cout
• From the truth table we can write the Boolean
  equation for the S and Cout
• Simplify using Boolean Algebra and K-map we get

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Sum Any 2 of the three inputs are 1Cout XOR
between A B Cin
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Full Adder diagram
31
Half Subtractor
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What is a Half Subtractor

• A logic gate that perform 1 bit subtraction
• When 0-1 occurs a carry produces 1

33
Half Subtractor
C
A
B
D
0
0
0
1
0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0
2
1
0 -1 1
34
Half Subtractor

• Operation A - B

35
Full Subtractor
36
What is a Full Subtraction

• Logic gates that perform two bits subtraction

37
Full Subtractor
Ci Ai Bi Di Ci1
0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1
0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1
1
1
1
1
Di
38
Full Subtractor
Ci Ai Bi Di Ci1
0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1
0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1
1
1
1
1
Ci1
Ci1 !Ai Bi Ci !Ai !Bi Ci
Ai Bi
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Full Subtractor
Ci1 !Ai Bi Ci !Ai !Bi Ci
Ai Bi
Ci1 !Ai Bi Ci (!Ai !Bi Ai
Bi) Ci1 !Ai Bi Ci !(Ai Bi)
Recall
Di Ci (Ai Bi)
Ci1 !Ai Bi Ci !(Ai Bi)
40
Full Subtractor
Di Ci (Ai Bi)
Ci1 !Ai Bi Ci !(Ai Bi)
41
Full Subtractor

• Operation A - B - Bin

42
Adder/Subtractor - 1
Half subtractor
Half adder
E 0 Half adder
E 1 Half subtractor
43
Adder/Subtractor-1
i1
E 0 Full adder E 1 Full subtractor
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Reordered Full Adder
Full Adder
Ci Ai Bi Si Ci1
Ci Ai Bi Si Ci1
0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1
0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0
0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0
NOT
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Making a full subtractor from a full adder
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Four-Bit Parallel Adder

• This circuit is sometimes referred to as a
  ripple-through adder
• C0 ripples through four two-level logic circuits
  and hence the sum cannot be completed until eight
  gate delays
• For this kind of adder the maximum delay is
  directly proportional to the number of stages n.

47
Adder/Subtractor-2
E 0 4-bit adder E 1 4-bit subtractor
48
Carry Look-Ahead Circuit

• To improve the speed of addition
• Consider the carry output equation for a full
  adder is
• Which can be expressed as follows
• or as
• where

49
Carry Look-Ahead Circuit

• Four a four-bit adder the generate and propagate
  terms for each stage are
• while the carries for the various stages are

50
Carry Look-Ahead Circuit

• Substituting for C0 in the C1 equation etc leads
  to the following equations
• And the sum
• Since the number of levels of logic required when
  a large number of bits has to be added does not
  increase then the Carry Look-Ahead adder will
  provide a faster addition time

51
Binary Multiplication

• Paper and Pen method
• which is implemented using
• 9 AND gates 3 FA and
• 3 HA