This lecture note has been summarized from lecture note on Introduction to VLSI ... Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com ... – PowerPoint PPT presentation
This lecture note has been summarized from lecture note on Introduction to VLSI Design VLSI Circuit Design all over the world. I cant remember where thosecome from. However Id like to thank all professors who create such a good work on those lecture notes. Without those lectures thiscant be finished.
3 Todays Topics
Course overview
Objectives
Roadmap for the Semester
Administrative Details
VLSI Overview
Transistor Structure
Static CMOS Logic
Design Methods Design Styles
VLSI Trends
4 Course Objectives (1/3)
Students should be able to
VLSI Circuit Analysis
Understand MOS transistor operation design eqns.
Understand parasitics perform simple calculations
Understand static dynamic CMOS logic
Estimate delay of CMOS gates networks long wires
Estimate power consumption
Understand design and operation of latches flip/flops
5 Course Objectives (2/3)
CMOS Processing and Layout
Understand the VLSI manufacturing process.
Have an appreciation of current trends in VLSI manufacturing.
Understand layout design rules.
Design and analyze layouts for simple digital CMOS circuits
Design and analyze hierarchical circuit layouts.
Understand ASIC Layout styles.
6 Course Objectives (3/3)
VLSI System Design
Understand register-transfer level design.
Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL).
Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL.
Understand the design flows used in industrial IC design.
Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation.
7 Roadmap for the term major topics
VLSI Overview
CMOS Processing Fabrication
Components Transistors Wires Parasitics
Design Rules Layout
Combinational Circuit Design Layout
Sequential Circuit Design Layout
Standard-Cell Design with CAD Tools Verilog
Mixed Signal Concerns D/A A/D Conversion
Design Project Complete Chip
8 VLSI Overview
Why Make IC
IC Evolution
Common technologies
CMOS Transistors Logic Gates
Structure
Switch-Level Transistor Model
Basic gates
The VLSI Design Process
Levels of Abstraction
Design steps
Design styles
VLSI Trends
9 Why Make ICs
Integration improves
size
speed
power
Integration reduce manufacturing costs
(almost) no manual assembly
10 IC Evolution (1/3)
SSI Small Scale Integration (early 1970s)
contained 1 10 logic gates
MSI Medium Scale Integration
logic functions counters
LSI Large Scale Integration
first microprocessors on the chip
VLSI Very Large Scale Integration
now offers 64-bit microprocessors complete with cache memory (L1 and often L2) floating-point arithmetic unit(s) etc.
11 IC Evolution (2/3)
Bipolar technology
TTL (transistor-transistor logic)
ECL (emitter-coupled logic)
MOS (Metal-oxide-silicon)
although invented before bipolar transistor was initially difficult to manufacture
nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps was denser and consumed less power than equivalent bipolar ICs gt an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market.
12 IC Evolution (3/3)
aluminum gates for replaced by polysilicon by early 1980
CMOS (Complementary MOS) n-channel and p-channel MOS transistors gt lower power consumption simplified fabrication process
Bi-CMOS - hybrid Bipolar CMOS (for high speed)
GaAs - Gallium Arsenide (for high speed)
Si-Ge - Silicon Germanium (for RF)
13 (No Transcript) 14 VLSI Technology - CMOS Transistors 2002 L130nm 2003 L90nm 2005 L65nm 15 Transistor Switch Model
NFET or n transistor
on when gate H
good switch for logic L
poor switch for logic H
pull-down device
PFET or p transistor
on when gate L
good switch for logic H
poor switch for logic L
pull-up device
16 CMOS Logic Design
Complementary transistor networks
Pullup p transistors
Pulldown - n transistors
17 CMOS Inverter Operation 18 CMOS Logic Example - Whats This 19 VLSI Levels of Abstraction Specification (what the chip does inputs/outputs) Architecture major resources connections Register-Transfer logic blocks FSMs connections Logic gates flip-flops latches connections Circuit transistors parasitics connections Layout mask layers polygons 20 The VLSI Design Process
Move from higher to lower levels of abstraction
Use CAD tools to automate parts of the process
Use hierarchy to manage complexity
Different design styles trade off
Design time
Non-recurring engineering (NRE) cost
Unit cost
Performance
Power Consumption
21 VLSI Design Tradeoffs (1/2)
Non-Recurring Engineering (NRE) Costs
Design Costs
Mask Tooling costs
Unit Cost - related to chip size
Amount of logic
Current technology
Performance
Clock speed
Implementation
22 VLSI Design Tradeoffs (2/2)
Power consumption - a relatively new concern
Power supply voltage
Clock speed
23 VLSI Design Styles
Full Custom
Application-Specific Integrated Circuit (ASIC)
Programmable Logic (PLD FPGA)
System-on-a-Chip
24 Full Custom Design
Each circuit element carefully handcrafted
Huge design effort
High Design NRE Costs / Low Unit Cost
High Performance
Typically used for high-volume applications
25 Application-Specific Integrated Circuit (ASIC)
Constrained design using pre-designed (and sometimes pre-manufactured) components
Also called semi-custom design
CAD tools greatly reduce design effort
Low Design Cost / High NRE Cost / Med. Unit Cost
Medium Performance
26 Programmable Logic (PLDs FPGAs)
Pre-manufactured components with programmable interconnect
Typical use calculator first microcomputer chip arithmetic manipulation
50 Gallery - Current Processors 51 Gallery - Current Processors 52 Pentium 4
0.18-micron process technology (2 1.9 1.8 1.7 1.6 1.5 and 1.4 GHz)
Introduction date August 27 2001 (2 1.9 GHz) ... November 20 2000 (1.5 1.4 GHz)
Level Two cache 256 KB Advanced Transfer Cache (Integrated)
System Bus Speed 400 MHz
SSE2 SIMD Extensions
Transistors 42 Million
Typical Use Desktops and entry-level workstations
0.13-micron process technology (2.53 2.2 2 GHz)
Introduction date January 7 2002
Level Two cache 512 KB Advanced
Transistors 55 Million
53 Intels McKinley
Introduction date Mid 2002
Caches 32KB L1 256 KB L2 3MB L3 (on-chip)
Clock 1GHz
Transistors 221 Million
Area 464mm2
Typical Use High-end servers
Future versions5GHz 0.13-micron technology
54 Gallery - Current FPGA 55 Gallery - Graphics Processor 56 What were going to do
Chip design MOSIS tiny chip
57 What were going to do
Fabricated MOSIS Tiny Chip
58 Die Photo - 2001 Design Project Chip Design by Ed Thomas Photo courtesy Ron Feiller Agere
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