ECE 434 Advanced Digital System L04

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ECE 434Advanced Digital SystemL04

• Electrical and Computer EngineeringUniversity of
  Western Ontario

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Outline

• What we know
• Combinational Networks
• Analysis
• Synthesis
• AND-OR-NOTs, NORs, NANDs, MUXes, ROMs, PLAs
• Hazards in combinational networks
• What we do not know
• PALs
• Sequential Networks
• Basic Building Blocks
• Mealy Sequential Networks

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Review Basic ROM Structure

• ROM Types
• Mask-programmable ROM
• EPROM
• EEPROM
• Flash

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Review Programmable Logic Arrays

• Perform the same function as a ROM
• n inputs and m outputs m functions of n
  variables
• AND array realizes product terms of the input
  variables
• OR array ORs together the product terms

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Review PLA with 3 inputs, 5 p.t., 4 outputs
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Programmable Array Logic (PALs)

• PLAs
• Both AND and OR arrays are programmable
• PAL is a special case of PLA
• AND array is programmable and OR array is fixed
• Motivation for PALs
• Programmable switches historically presented two
  difficulties to the manufacturers
• hard to fabricate correctly gt increase the price
• reduce the speed performance of circuits
• PALs are less expensive, faster, and easier to
  program
• Disadvantage less flexible

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Programmable Array Logic (PALs)
Unprogrammed
Programmed
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Using PALs An Example
x
x
x
1
2
3
Implement the following
P
1
P
2
P
3
P
4
AND plane
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Using PALs An Example
x
x
x
1
2
3
P
1
f
1
P
2
P
3
f
2
P
4
AND plane
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Typical PALs

• Typical PALs have
• from 10 to 20 inputs
• from 2 to 10 outputs
• from 2 to 8 AND gates driving each OR gate
• often include D flip-flops

MUX output is fed back to the AND plane. Why?
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Logic Diagram for 16R4 PAL
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Logic Diagram for 16R4 PAL
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Sequential Networks

• Have memory (state)
• Present state depends not only on the current
  input, but also on all previous inputs (history)
• Future state depends on the current input and
  state

X x1 x2... xn
Q Q1 Q2... Qk
Z z1 z2... zm
x1
z1
x2
z2
Q
Flip-flops are commonly used as storage
devicesD-FF, JK-FF, T-FF
xn
zm
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Clocked D Flip-Flop with Rising-edge Trigger
Next state
The next state in response to the rising edge of
the clock is equal to the D input before the
rising edge
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Clocked JK Flip-Flop
Next state
JK 00 gt no state change occurs JK 10 gt the
flip-flop is set to 1, independent of the current
state JK 01 gt the flip-flop is always reset to
0 JK 11 gt the flip-flop changes the state Q
Q
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Clocked JK Flip-Flop
Next state
T 1 gt the flip-flop changes the state Q
Q T 0 gt no state change
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S-R Latch
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Transparent D Latch
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Transparent D Latch
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Mealy Sequential Networks
General model of Mealy Sequential Network

• (1) X inputs are changed to a new value
• After a delay, the Z outputs and next state
  appear at the output of CM
• (3) The next state is clocked into the state
  register and the state changes

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An Example 8421 BCD to Excess3 BCD Code Converter
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State Graph and Table for Code Converter
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State Assignment Rules
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Transition Table
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K-maps
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Realization
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To Do

• Study textbook chapters
• 3.1, 3.2, 3.3, 1.6, 1.7
• Do homework 1