Combinational Design

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Combinational Design

• Chapter 6, Sections 6-10
• 6.6 Three-state devices
• 6.7 Multiplexers
• 6.8 EXOR and Parity Circuits
• 6.9 Comparators
• 6.10 Adders, Subtractors and ALUs

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• Three-state devices and buses
• 6.5

3
Three-state buffers inverting and non-inverting
enable, inverting and non-inverting output
4
Eight sources sharinga three-state party line
5
Timing diagram for party line Data should be
asserted or negated during enable window
6
74x541 octalthree-state buffer
7
74x541 for a microprocessor input port selects
one of two user inputs
8
Bidirectional octal 3-statetransceiver
A?B B?A G_L 0 0 DIR 1 0
Note hysteresis symbolON after OFF
t
9
Bus transfer A to B orB to A
10
Control signals for a pair of bidirectional buses
11
Four two-bit buses!
Bus-DRIVER jargon
All the buses are driven either by a constant,or
by one of the other buses. The source bus is
driven with 00.
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PLD I/O for four 2-bit buses. OE are individual
output enable signals. MOE is the master output
enable signal.
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• MULTIPLEXERS
• 6.7

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What is a mux?

• A mux is a digital switch that connects one of n
  inputs to its single output.
• The Inputs can be one or more bits wide.
• A Control signal selects the active input.
• An Enable signal enables the mux to do its thing.
• A demultiplexer does the opposite it routes a
  signal to one of several destinations.

15
A mux with n sources,each b bits wide.
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21, 41, 81 MUXes
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Cascading MUXes
Z
0
1
S
A
C
B
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74x151 8-input, 1-bit mux
enable
output
inputs
select 101
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Truth table for a 74x157 2-input, 4-bit
multiplexer
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74x157 2-input, 4-bit multiplexer
Note that inputpins are interlaced
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Combining a decoder with 4 74x151s for a31-to-1
mux XA0 XA4 select 151 This can be one
bit of 32 32-bit registers
A, B, C are SELECT lines Note EN_LO
QUIZ NEXT
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QUIZ Suppose XA 1A Input F0E4 AD00 XOUT
?
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SOLUTION Suppose XA 1A 26 11
010 Input F0E4 AD00 Bits 24-27 all 0 XOUT
0
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Buffers to increase fanout from 8 to 160. Needed
for select signals.
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Demultiplexers (DEMUX)
Opposite of MUX

• Demux single data input, n control inputs, 2n
  outputs
• control inputs (called selects S) represent
  binary index of output to which the input is
  connected
• data input usually called "enable" (G)
• Usually Enable G 1

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Another bus driver
Equivalentswitch
Block diagram
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Using a 3-to-8 binary decoder as a 1-bit,
8-output demux
(the data is on the GO pin!)
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GAL16V8 masquerading as a 2-input, 4-bit mux
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A 2n-1-input, 1-bit mux can implement any logic
function of n variables!
Here is an OR
0 1 1 1
00 0 01 1 10 1 11 1
221 MUX
select lines correspond to rows in the truth table
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Implementing Logic with MUX

• 2n-1 1 multiplexer can implement any Boolean
  function of n variables
• needs n-1 control variables the remaining
  variable is used as a data input to the
  multiplexer
• Example
• F(A,B,C) m0 m2 m6 m7
• A' B' C' A' B C' A B C' A B C
• A' B' (C') A' B (C') A B' (0) A B
  (1)
• (clever!)

QUIZ
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Example
1
0
0
1
1
2
A
B
C
F
F
81
0
3
MUX
0
0
0
0
1
4
0
5
0
0
1
0
1
6
1
7
S2 S1 S0
0
1
0
1
A
B
C
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
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QUIZ
FAB BC ABC
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QUIZ SOLUTIONFABBCABC
F 0 0 1 1 1 0 0 1
0 1 2 3
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Logic can also be done with a decoder OR gates
Enb 1
A
B
C
D
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Mux summary

• Muxes are data switches
• They can switch more than one bit
• They route incoming data to a selected output
• They can realize arbitrary logic functions
• Demuxes distribute data from one source to n
  outputs
• They too can switch more than one bit
• Like most combinational circuits, both can be
  realized with PLDs

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• EXCLUSIVE OR and PARITY CIRCUITS
• 6.8

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Truth Table for XOR and XNOR
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QUIZ Which of these are XOR, which are XNOR, and
which are neither?
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Symbology (MS-Word thinks it should be Zymology)
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EXOR from AND/OR, from NAND3 gate delays XNOR
is faster!
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Daisy-chain and Tree structures
Which requires fewer gates?
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9-bit odd/even parity generator
Generalized XOR is ODD parity
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Parity generation and checking for an 8-bit wide
memory
During RD, odd parity signals ERROR
Bus driver
During write, ODD parity bit entered on PIN, and
stored.So there will be an even number of 1s in
the 9 stored bits.
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7-bit Hamming code error correction
NOERROR_L (ERROR)
Compute parity of thethree bit
groups Decoded non-zero value of
syndrome indicates which bit is in error
o 1
1
OUT
Decodesyndrome
Reverse if syndrome ? 0
Output of XOR with one input1 is complement of
other input
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COMPARATORS with EXOR gates
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• You have until Wednesday to negotiate MT1 grades.
• Either find grader or write a note.

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Wide OR
ORs
NORs and NAND is faster!
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ITERATIVE combinational circuit
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ITERATIVE COMPARATOR
XNOR gate EQUIVALENCE gate
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74x85 4-bit ITERATIVE COMPARATOR
lessequalgreater
lessequalgreater from lower- order bits
OUT
IN
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12-bit iterative comparator
8-11
4-7
0-3
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8-bit parallel comparator gate diagram
equivalence gates
PEQQ_L
if more sig bits , and pi qi, the PQ
PGTQ_L
p1, q0
MSB q q
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74x682 8-bit comparator
only two outputs if both false (11), then PLTQ
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?
EQUAL and GREATER are enough!
samecomparator
E.g., if P Q, OR P Q, then P Q
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QUIZ PEQQ PGTQ

• F(PEQQ, PGTQ)
• P?Q PEQQ
• PQ
• PQ PGQQ PEQQ
• PQ
• P
• PQ

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PEQQ PGTQ

• P?Q PEQQ
• PQ PGTQ
• PQ PGQQ PEQQ
• PQ PEQQ
• PQ PGTQ

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COMPARATIVE SUMMARY

• EXORs are used for parity checking because
• the EXOR of an odd number of 1s is 1. (W?X)
  (Y?Z) ? W ? X ? Y ? Z
• (W?X) (Y?Z) ? W ? X ? Y ? Z
• (W?X) ? (Y?Z) W ? X ? Y ? Z
• Parity in memory is generated on WRITE, and
  checked on READ (and corrected).
• It is equally easy to determine whether two words
  are equal or unequal.
• Comparators are either parallel or iterative.
• Two outputs suffice to determine arithmetic
  comparisons.